公开(公告)号：EP1378090A4

公开(公告)日：2005-02-09

申请号：EP02723233

申请日：2002-02-25

Applicant: IBM

Inventor： BARRETT WAYNE M ,  CHEN DONG ,  COTEUS PAUL W ,  GARA ALAN G ,  JACKSON RORY D ,  KOPCSAY GERARD V ,  NATHANSON BEN J ,  TAKKEN TODD E ,  VRANAS PAVLOS M

IPC: G06F11/10 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/20 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F13/00 ,  G06F13/24 ,  G06F13/38 ,  G06F15/173 ,  G06F15/177 ,  G06F15/80 ,  G06F17/14 ,  H04L1/00 ,  H04L7/02 ,  H04L7/033 ,  H04L12/28 ,  H04L12/56 ,  H04L25/02 ,  H05K7/20 ,  H04L7/00 ,  H03D3/24 ,  H04B10/08

CPC classification number: H05K7/20836 ,  F24F11/77 ,  G06F9/52 ,  G06F9/526 ,  G06F15/17381 ,  G06F17/142 ,  G09G5/008 ,  H04L7/0338 ,  Y02B30/746

Abstract: A fan module including: two or more individual fans, each fan having an air movement means and a motor engaged with the air movement means for accelerating air entering each of the two or more individual fans; a temperature sensor for sensing a temperature associated with the two or more fans and for outputting a first signal corresponding to the temperature; rotational speed sensor for outputting a second signal corresponding to a rotational speed of each of the two or more fans; and a processor for receiving the first and second signals and controlling the two or more individual fans based on the first and second signals.

公开(公告)号：CA2436413C

公开(公告)日：2011-09-27

申请号：CA2436413

申请日：2002-02-25

Applicant: IBM

Inventor： BHANOT GYAN V ,  BLUMRICH MATTHIAS A ,  CHEN DONG ,  COTEUS PAUL W ,  GARA ALAN G ,  GIAMPAPA MARK E ,  HEIDELBERGER PHILIP ,  STEINMACHER-BUROW BURKHARD D ,  TAKKEN TODD E ,  VRANAS PAVLOS M

IPC: G06F11/10 ,  H04L1/18 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/20 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F13/00 ,  G06F13/24 ,  G06F13/38 ,  G06F15/173 ,  G06F15/177 ,  G06F15/80 ,  G06F17/14 ,  H04J3/02 ,  H04L1/00 ,  H04L7/02 ,  H04L7/033 ,  H04L12/28 ,  H04L12/56 ,  H04L25/02 ,  H05K7/20

Abstract: Class network routing is implemented in a network such as a computer network comprising a plurality of parallel compute processors at nodes thereof. Class network routing allows a compute processor to broadcast a message to a range (one or more) of other compute processors in the computer network, such as processors in a column or a row. Normally this type of operation requires a separate message to be sent to each processor. With class network routing pursuant to the invention, a single message is sufficient, which generally reduces the total number of messages in the network as well as the latency to do a broadcast, Class network routing is also applied to dense matrix inversion algorithms on distributed memory parallel supercomputers with hardware class function (multicast) capability. This is achieved by exploiting the fact that the communication patterns of dense matrix inversion can be served by hardware class functions, which results in faster execution times.

公开(公告)号：AT469501T

公开(公告)日：2010-06-15

申请号：AT02721138

申请日：2002-02-25

Applicant: IBM

Inventor： CHEN DONG ,  COTEUS PAUL W ,  GARA ALAN G ,  GIAMPAPA MARK E ,  TAKKEN TODD E

IPC: G06F11/10 ,  H04L29/12 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/20 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F13/00 ,  G06F13/24 ,  G06F13/38 ,  G06F15/173 ,  G06F15/177 ,  G06F15/80 ,  G06F17/14 ,  H04L1/00 ,  H04L7/02 ,  H04L7/033 ,  H04L12/28 ,  H04L12/56 ,  H04L25/02 ,  H05K7/20

Abstract: In a massively parallel system, a method and apparatus for uniquely assigning a MAC address(400) to a device encodes the MAC address with a physical location of the device(410). The method and apparatus include configuring device interconnections of the parallel system with physical topological information such as a rack number, a midplane number, a card number, and a chip number. A device or node with a physical location encoded MAC address may then be interrogated by location for test, diagnostic, and program loading purposes.

公开(公告)号：CA2437035C

公开(公告)日：2009-01-06

申请号：CA2437035

申请日：2002-02-25

Applicant: IBM

Inventor： COTEUS PAUL W ,  CHEN DONG ,  BLUMRICH MATTHIAS A ,  GARA ALAN G ,  HEIDELBERGER PHILIP ,  TAKKEN TODD E ,  GIAMPAPA MARK E ,  STEINMACHER-BUROW BURKHARD D ,  KOPSCAY GERARD V

IPC: G06F11/10 ,  G06F15/173 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/20 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F13/00 ,  G06F13/24 ,  G06F13/38 ,  G06F15/177 ,  G06F15/76 ,  G06F15/80 ,  G06F17/14 ,  H04L1/00 ,  H04L7/02 ,  H04L7/033 ,  H04L12/28 ,  H04L12/56 ,  H04L25/02 ,  H05K7/20

Abstract: A system and method for generating global asynchronous signals in a computin g structure. Particularly, a global interrupt and barrier network is implement ed that implements logic for generating global interrupt and barrier signals fo r controlling global asynchronous operations perfomed by processing elements a t selected processing nodes (12) of computing structure in accordance with a processing algorithm; and includes the physical interconnecting of the processing nodes (12) for communicating the global interrupt and barrier signals to the elements via low latency paths. The global asynchronous signa ls respectively initiate interrupt and barrier operations at the processing nod es (12) at times selected for otpimizing performance of the processing algorithms. In one embodiment, the global interrupt and barrier network is implemented in a scalable, massively parallel supercomputing device structur e comprising a plurality of processing nodes interconnected by multiple independent networks.

公开(公告)号：CA2436474A1

公开(公告)日：2002-09-06

申请号：CA2436474

申请日：2002-02-25

Applicant: IBM

Inventor： COTEUS PAUL W ,  BLUMRICH MATTHIAS A ,  CHEN DONG ,  GARA ALAN G ,  HOENICKE DIRK ,  OHMACHT MARTIN ,  VRANAS PAVLOS M ,  TAKKEN TODD E ,  STEINMARCHER-BUROW BURKHARD D ,  GIAMPAPA MARK E ,  HEIDELBERGER PHILIP

IPC: G06F11/10 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/20 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F12/14 ,  G06F13/00 ,  G06F13/24 ,  G06F13/38 ,  G06F15/173 ,  G06F15/177 ,  G06F15/80 ,  G06F17/14 ,  H04L1/00 ,  H04L7/02 ,  H04L7/033 ,  H04L12/28 ,  H04L12/56 ,  H04L25/02 ,  H05K7/20

Abstract: A low latency memory system access is provided in association with a weakly- ordered multiprocessor system(Fig.1). Each processor(12-1, 12-2) in the multiprocessor shares resources, and each shared resource has an associated lock within a locking device(10) that provides support for synchronization between the multiple processors(12-1, 12-2) in the multiprocessor and the orderly sharing of the resources. A processor(12-1, 12-2) only has permissio n to access a resource when it owns the lock associated with that resource, an d an attempt by a processor(12-1, 12-2) to own a l ock requires only a single load operation, rather than a traditional atomic load followed by store, suc h that the processor(12-1, 12-2) only performs a read operation and the hardwa re locking device(10) performs a subsequent write operation rather than the processor(12-1, 12-2).

公开(公告)号：DE60236510D1

公开(公告)日：2010-07-08

申请号：DE60236510

申请日：2002-02-25

Applicant: IBM

Inventor： CHEN DONG ,  COTEUS PAUL W ,  GARA ALAN G ,  GIAMPAPA MARK E ,  TAKKEN TODD E

IPC: G06F11/10 ,  G06F15/16 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/20 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F13/00 ,  G06F13/24 ,  G06F13/38 ,  G06F15/173 ,  G06F15/177 ,  G06F15/80 ,  G06F17/14 ,  H04L1/00 ,  H04L7/02 ,  H04L7/033 ,  H04L12/28 ,  H04L12/56 ,  H04L25/02 ,  H05K7/20

公开(公告)号：CA2438195C

公开(公告)日：2009-02-03

申请号：CA2438195

申请日：2002-02-25

Applicant: IBM

Inventor： COTEUS PAUL W ,  GARA ALAN G ,  CHEN DONG ,  BLUMRICH MATTHIAS A ,  VRANAS PAVLOS M ,  TAKKEN TODD E ,  STEINMACHER-BUROW BURKHARD D ,  HEIDELBERGER PHILIP ,  GIAMPAPA MARK E

IPC: G06F11/10 ,  G06F15/173 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/20 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F13/00 ,  G06F13/24 ,  G06F13/38 ,  G06F15/177 ,  G06F15/80 ,  G06F17/14 ,  H04L1/00 ,  H04L7/02 ,  H04L7/033 ,  H04L12/28 ,  H04L12/54 ,  H04L12/56 ,  H04L25/02 ,  H05K7/20

Abstract: In a massively parallel computing system having a plurality of nodes configured in m multi-dimensions, each node including a computing device, a method for routing packets towards their destination nodes is provided which includes generating at least one of a 2m plurality of compact bit vectors (115, 154) containing information derived from downstream nodes. A multileve l arbitration process (116, 155) in which downstream information stored in the compact vectors, such as link status information and fullness of downstream buffers (130, 140), is used to determine a preferred direction and virtual channel for packet transmission. Preferred direction ranges are encoded and virtual channels are selected by examining the plurality of compact bit vectors (115, 154). This dynamic routing method eliminates the necessity of routing tables, thus enhancing scalability of the switch.

公开(公告)号：CA2436395A1

公开(公告)日：2002-09-06

申请号：CA2436395

申请日：2002-02-25

Applicant: IBM

Inventor： GIAMPAPA MARK E ,  GARA ALAN G ,  COTEUS PAUL W ,  TAKKEN TODD E ,  CHEN DONG

IPC: G06F11/10 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/20 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F13/00 ,  G06F13/24 ,  G06F13/38 ,  G06F15/173 ,  G06F15/177 ,  G06F15/80 ,  G06F17/14 ,  H04L1/00 ,  H04L7/02 ,  H04L7/033 ,  H04L12/28 ,  H04L12/56 ,  H04L25/02 ,  H05K7/20 ,  G06F15/16

Abstract: In a massively parallel system, a method and apparatus for uniquely assignin g a MAC address(400) to a device encodes the MAC address with a physical location of the device(410). The method and apparatus include configuring device interconnections of the parallel system with physical topological information such as a rack number, a midplane number, a card number, and a chip number. A device or node with a physical location encoded MAC address m ay then be interrogated by location for test, diagnostic, and program loading purposes.

公开(公告)号：ES2346409T3

公开(公告)日：2010-10-15

申请号：ES02721138

申请日：2002-02-25

Applicant: IBM

Inventor： CHEN DONG ,  COTEUS PAUL W ,  GARA ALAN G ,  GIAMPAPA MARK E ,  TAKKEN TODD E

IPC: G06F11/10 ,  H04L29/12 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/20 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F13/00 ,  G06F13/24 ,  G06F13/38 ,  G06F15/173 ,  G06F15/177 ,  G06F15/80 ,  G06F17/14 ,  H04L1/00 ,  H04L7/02 ,  H04L7/033 ,  H04L12/28 ,  H04L12/56 ,  H04L25/02 ,  H05K7/20

Abstract: Procedimiento para asignar, de manera única, una dirección MAC (400) a un dispositivo de computación en un nodo (205) de un sistema de computación masivamente paralelo que comprende una pluralidad de dichos nodos, caracterizado porque el procedimiento comprende: programar el dispositivo de computación para codificar una ubicación física del dispositivo de computación en la dirección MAC; usar un número predeterminado de bits (410) de la dirección MAC para la etapa de codificación, en la que la ubicación física del dispositivo de computación es descrita de manera única.

公开(公告)号：DE60237433D1

公开(公告)日：2010-10-07

申请号：DE60237433

申请日：2002-02-25

Applicant: IBM

Inventor： BLUMRICH MATTHIAS A ,  CHEN DONG ,  CHIU GEORGE L ,  CIPOLLA THOMAS M ,  COTEUS PAUL W ,  GARA ALAN G ,  GIAMPAPA MARK E ,  HEIDELBERGER PHILIP ,  KOPSCAY GERALD V ,  MOK LAWRENCE S ,  TAKKEN TODD E

IPC: G06F11/10 ,  G06F15/16 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/20 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F13/00 ,  G06F13/24 ,  G06F13/38 ,  G06F15/00 ,  G06F15/173 ,  G06F15/177 ,  G06F15/80 ,  G06F17/14 ,  H04L1/00 ,  H04L7/02 ,  H04L7/033 ,  H04L12/28 ,  H04L12/56 ,  H04L25/02 ,  H05K7/20