公开(公告)号：DE602005009494D1

公开(公告)日：2008-10-16

申请号：DE602005009494

申请日：2005-07-06

Applicant: SONY COMPUTER ENTERTAINMENT INC ,  IBM

Inventor： DAY MICHAEL NORMAN ,  JOHNS CHARLES RAY ,  LIU PEICHUN PETER ,  TRUONG THUONG QUANG ,  YAMAZAKI TAKESHI

IPC: G06F13/28

Abstract: A method, an apparatus, and a computer program are provided for controlling memory access. Direct Memory Access (DMA) units have become commonplace in a number of bus architectures. However, managing limited system resources has become a challenge with multiple DMA units. In order to mange the multitude of commands generated and preserve dependencies, embedded flags in commands or a barrier command are used. These operations then can control the order in which commands are executed so as to preserve dependencies.

公开(公告)号：HK1070719A1

公开(公告)日：2005-06-24

申请号：HK05103951

申请日：2005-05-11

Applicant: IBM

Inventor： DAY MICHAEL N ,  JOHNS CHARLES R ,  KAHLE JAMES A ,  LIU PEICHUM P ,  TRUONG THUONG QUANG

IPC: G06F20060101 ,  G06F12/08 ,  G06F9/46 ,  G06F13/14 ,  G06F13/28

Abstract: The present invention provides for atomic update primitives in an asymmetric single-chip heterogeneous multiprocessor computer system having a shared memory with DMA transfers. At least one lock line command is generated from a set comprising a get lock line command with reservation, a put lock line conditional command, and a put lock line unconditional command.

公开(公告)号：CA2505610A1

公开(公告)日：2004-06-24

申请号：CA2505610

申请日：2003-11-21

Applicant: IBM

Inventor： KAHLE JAMES ALLAN ,  TRUONG THUONG QUANG ,  JOHNS CHARLES RAY ,  SHIPPY DAVID ,  HOFSTEE HARM PETER ,  DAY MICHAEL NORMAN

IPC: G06F12/10 ,  G06F12/12

Abstract: Memory management in a computer system is improved by preventing a subset of address translation information from being replaced with other types of address translation information in a cache memory reserved for storing such address translation information for faster access by a CPU. This way, the CP U can identify the subset of address translation information stored in the cac he.

公开(公告)号：DE60320026T2

公开(公告)日：2009-05-14

申请号：DE60320026

申请日：2003-11-21

Applicant: IBM

Inventor： DAY MICHAEL NORMAN ,  HOFSTEE HARM PETER ,  JOHNS CHARLES RAY ,  KAHLE JAMES ALLAN ,  TRUONG THUONG QUANG ,  SHIPPY DAVID

IPC: G06F12/10 ,  G06F12/12

Abstract: Memory management in a computer system is improved by preventing a subset of address translation information from being replaced with other types of address translation information in a cache memory reserved for storing such address translation information for faster access by a CPU. This way, the CPU can identify the subset of address translation information stored in the cache.

公开(公告)号：DE60320026D1

公开(公告)日：2008-05-08

申请号：DE60320026

申请日：2003-11-21

Applicant: IBM

Inventor： DAY MICHAEL NORMAN ,  HOFSTEE HARM PETER ,  JOHNS CHARLES RAY ,  KAHLE JAMES ALLAN ,  TRUONG THUONG QUANG ,  SHIPPY DAVID

IPC: G06F12/10 ,  G06F12/12

Abstract: Memory management in a computer system is improved by preventing a subset of address translation information from being replaced with other types of address translation information in a cache memory reserved for storing such address translation information for faster access by a CPU. This way, the CPU can identify the subset of address translation information stored in the cache.

公开(公告)号：AU2003302824A8

公开(公告)日：2004-06-30

申请号：AU2003302824

申请日：2003-11-21

Applicant: IBM

Inventor： JOHNS CHARLES RAY ,  TRUONG THUONG QUANG ,  HOFSTEE HARM PETER ,  SHIPPY DAVID ,  KAHLE JAMES ALLAN ,  DAY MICHAEL NORMAN

IPC: G06F12/10 ,  G06F12/12

Abstract: Memory management in a computer system is improved by preventing a subset of address translation information from being replaced with other types of address translation information in a cache memory reserved for storing such address translation information for faster access by a CPU. This way, the CPU can identify the subset of address translation information stored in the cache.

公开(公告)号：AU2003302824A1

公开(公告)日：2004-06-30

申请号：AU2003302824

申请日：2003-11-21

Applicant: IBM

Inventor： DAY MICHAEL NORMAN ,  HOFSTEE HARM PETER ,  JOHNS CHARLES RAY ,  KAHLE JAMES ALLAN ,  TRUONG THUONG QUANG ,  SHIPPY DAVID

IPC: G06F12/10 ,  G06F12/12

Abstract: Memory management in a computer system is improved by preventing a subset of address translation information from being replaced with other types of address translation information in a cache memory reserved for storing such address translation information for faster access by a CPU. This way, the CPU can identify the subset of address translation information stored in the cache.