公开(公告)号：CA773730A

公开(公告)日：1967-12-12

申请号：CA773730D

Applicant: IBM

Inventor： WALDECKER DONALD E

公开(公告)号：DE69325566T2

公开(公告)日：2000-01-27

申请号：DE69325566

申请日：1993-12-27

Applicant: IBM

Inventor： KAHLE JAMES A ,  KAU CHIN-CHENG ,  OGDEN AUBREY D ,  POURSEPANJ ALI A ,  KANG-GUO TU PAUL ,  WALDECKER DONALD E

IPC: G06F9/38

公开(公告)号：CA2112995A1

公开(公告)日：1994-07-09

申请号：CA2112995

申请日：1994-01-06

Applicant: IBM

Inventor： KAU CHIN-CHENG ,  OGDEN AUBREY D ,  WALDECKER DONALD E

IPC: G06F9/38 ,  G06F9/30

Abstract: METHOD AND SYSTEM FOR INDEXING THE ASSIGNMENT OF INTERMEDIATE STORAGE BUFFERS IN A SUPERSCALAR PROCESSOR SYSTEM A method and system for enhanced instruction dispatch efficiency in a superscalar processor system having a plurality of intermediate storage buffers, a plurality of general purpose registers, and a storage buffer index. Multiple scalar instructions may be simultaneously dispatched from a dispatch buffer to a plurality of execution units. Each of the multiple scalar instructions generally include at least one source operand and one destination operand. A particular one of the plurality of intermediate storage buffers is assigned to a destination operand within a selected one of the multiple scalar instructions. A relationship between the particular one of the plurality of intermediate storage buffers and a designated one of the plurality of general purpose registers is stored in the storage buffer index at that time when the instruction which has been dispatched is replaced in the dispatcher by another instruction in the application program sequence. Results of execution from the selected one of the multiple scalar instructions are stored in the particular one of the intermediate storage buffers when the selected instruction is executed. The storage buffer index is used to determine which storage buffers to use as source operands for those instructions which are dispatched between the time that a storage buffer has been assigned for a specific general purpose register and the results of execution are moved from the storage buffer into the general purpose register.

公开(公告)号：CA1225749A

公开(公告)日：1987-08-18

申请号：CA481595

申请日：1985-05-15

Applicant: IBM

Inventor： WALDECKER DONALD E ,  WRIGHT CHARLES G

IPC: G06F13/36 ,  G06F12/06 ,  G06F13/16 ,  G06F13/42 ,  G06F15/16 ,  G06F13/18

Abstract: AT9-84-011 DATA PROCESSING SYSTEM WITH A PLURALITY OF PROCESSORS ACCESSING A COMMON BUS TO INTERLEAVED STORAGE A plurality of data processor units are connected to a common bus which is connected to first and second interleaved storage units. The system is a synchronous one in which timing means establish a series of information transfer intervals. One or more of the processor units contain apparatus for selectively commencing an address transfer on the bus to one of the storage units during a transfer interval; the storage transaction initiated by the address transfer will require more than the one transfer interval to complete. One or more of the processors have means for monitoring the bus in order to determine whether an address on the bus has been transferred to the first or the second storage unit during a particular transfer interval. The address transfer apparatus further includes apparatus responsive to the monitoring apparatus for selectively transferring the next subsequent address to the other of said storage units to thus achieve alternating interleaving between storage units.

公开(公告)号：DE69322064T2

公开(公告)日：1999-07-01

申请号：DE69322064

申请日：1993-12-27

Applicant: IBM

Inventor： KAHLE JAMES A ,  KAU CHIN-CHENG ,  LEVITAN DAVID S ,  OGDEN AUBREY D ,  POURSEPANJ ALI A ,  KANG-GUO TU PAUL ,  WALDECKER DONALD E

IPC: G06F9/38

Abstract: A method and system for permitting single cycle instruction dispatch in a superscalar processor system which dispatches multiple instructions simultaneously to a group of execution units (24) for execution and placement of results thereof within specified general purpose registers (44, 46). Each instruction generally includes at least one source operand and one destination operand. A plurality of intermediate storage buffers (40, 42) are provided and each time an instruction is dispatched to an available execution unit (24), a particular one of the intermediate storage buffers (40, 42) is assigned to any destination operand within the dispatched instruction, permitting the instruction to be dispatched within a single cycle by eliminating any requirement for determining and selecting the specified general purpose register (44, 46) or a designated alternate general purpose register.

公开(公告)号：DE69321929D1

公开(公告)日：1998-12-10

申请号：DE69321929

申请日：1993-12-27

Applicant: IBM

Inventor： KAU CHIN-CHENG ,  OGDEN AUBREY D ,  WALDECKER DONALD E

IPC: G06F9/38

Abstract: A method and system for enhanced instruction dispatch efficiency in a superscalar processor system having intermediate storage buffers (60), general purpose registers (62), and a storage buffer index (58). A particular storage buffer (60) is assigned to a destination operand within a selected multiple scalar instruction. A relationship between the particular intermediate storage buffer (60) and a designated general purpose register (62) is stored in the storage buffer index (58) when the instruction which has been dispatched is replaced in the dispatcher by another instruction. Results of execution from the selected multiple scalar instruction are stored in the particular intermediate storage buffer (60) when the selected instruction is executed. The storage buffer index (58) is used to determine which storage buffers (60) to use as source operands for those instructions which are dispatched between the time that a storage buffer (58) has been assigned for a specific general purpose register (62) and the results of execution are moved from the storage buffer (60) into the general purpose register (62).

公开(公告)号：AT173345T

公开(公告)日：1998-11-15

申请号：AT93120943

申请日：1993-12-27

Applicant: IBM

Inventor： KAHLE JAMES A ,  KAU CHIN-CHENG ,  LEVITAN DAVID S ,  OGDEN AUBREY D ,  POURSEPANJ ALI A ,  KANG-GUO TU PAUL ,  WALDECKER DONALD E

IPC: G06F9/38

Abstract: A method and system for permitting single cycle instruction dispatch in a superscalar processor system which dispatches multiple instructions simultaneously to a group of execution units (24) for execution and placement of results thereof within specified general purpose registers (44, 46). Each instruction generally includes at least one source operand and one destination operand. A plurality of intermediate storage buffers (40, 42) are provided and each time an instruction is dispatched to an available execution unit (24), a particular one of the intermediate storage buffers (40, 42) is assigned to any destination operand within the dispatched instruction, permitting the instruction to be dispatched within a single cycle by eliminating any requirement for determining and selecting the specified general purpose register (44, 46) or a designated alternate general purpose register.

公开(公告)号：CA2107305A1

公开(公告)日：1994-07-09

申请号：CA2107305

申请日：1993-09-29

Applicant: IBM

Inventor： KAHLE JAMES A ,  WALDECKER DONALD E

IPC: G06F9/38 ,  G06F15/16

Abstract: A method and system for permitting nonsequential instruction dispatch in a superscalar processor system which dispatches sequentially ordered multiple instructions simultaneously to a group of execution units on an opportunistic basis for execution and placement of results thereof within specified general purpose registers. Each instruction generally includes at least one source operand and one destination operand. A plurality of intermediate storage buffers are provided and each time an instruction is dispatched to an available execution unit, a particular one of the intermediate storage buffers is assigned to any destination operand within the dispatched instruction, permitting the results of the execution of each instruction to be stored within an intermediate storage buffer. An indication of the status of each instruction is maintained within a completion buffer and thereafter utilized to selectively transfer results within the intermediate storage buffers to selected general purpose registers in an ordered consistent with an application specified sequential order. The occurrence of an interrupt which prohibits completion of a selected instruction can therefore be accurately identified within the completion buffer.

公开(公告)号：CA2107304A1

公开(公告)日：1994-07-09

申请号：CA2107304

申请日：1993-09-29

Applicant: IBM

Inventor： KAHLE JAMES A ,  KAU CHIN-CHENG ,  LEVITAN DAVID S ,  OGDEN AUBREY D ,  POURSEPANJ ALI A ,  TU PAUL K ,  WALDECKER DONALD E

IPC: G06F9/38 ,  G06F15/16

Abstract: A method and system for permitting single cycle instruction dispatch in a superscalar processor system which dispatches multiple instructions simultaneously to a group of execution units (24) for execution and placement of results thereof within specified general purpose registers (44, 46). Each instruction generally includes at least one source operand and one destination operand. A plurality of intermediate storage buffers (40, 42) are provided and each time an instruction is dispatched to an available execution unit (24), a particular one of the intermediate storage buffers (40, 42) is assigned to any destination operand within the dispatched instruction, permitting the instruction to be dispatched within a single cycle by eliminating any requirement for determining and selecting the specified general purpose register (44, 46) or a designated alternate general purpose register.

公开(公告)号：CA819928A

公开(公告)日：1969-08-05

申请号：CA819928D

Applicant: IBM

Inventor： HIGHBY LEONARD C JR ,  WALDECKER DONALD E