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公开(公告)号：CZ9800034A3
公开(公告)日：1998-11-11
申请号：CZ3498
申请日：1998-01-07
Applicant: IBM
Inventor： MACQUARRIE STEPHEN WESLEY , STORR WAYNE ROUSSELL , WILSON JAMES WARREN
IPC: H01L21/60 , H01L21/58 , H01L21/70 , H01L23/00 , H01L23/053 , H01L23/12 , H01L23/14 , H01L23/28 , H01L23/32 , H01L23/36 , H01L23/495 , H01L27/00 , H01L27/12
CPC classification number: H01L2224/48091 , H01L2224/48227 , H01L2924/01078 , H01L2924/14 , H01L2924/00014
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公开(公告)号：DE69305012T2
公开(公告)日：1997-04-03
申请号：DE69305012
申请日：1993-07-01
Applicant: IBM
IPC: H01L21/56 , H01L21/60 , H01L23/12 , H01L21/52 , H01L23/28 , H01L23/29 , H01L23/31 , H01L23/50 , H01L21/58
Abstract: A chip carrier is disclosed which includes a chip carrier substrate and at least one semiconductor chip mounted in a flip chip configuration, via solder balls, on a circuitized surface of the chip carrier substrate. The solder balls are encapsulated in a first encapsulant having a composition which includes an epoxy. In addition, at least a portion of the circuitry on the circuitized surface is encapsulated in a second encapsulant having a composition which includes a urethane, and which composition is chosen so that the second encapsulant exhibits a modulus of elasticity which is equal to or less than about 69.10 N/m . As a consequence, the second encapsulant exhibits neither internal cracks, nor interfacial cracks at the interface with the first encapsulant, nor does the second encapsulant delaminate from the circuitized surface, when the chip carrier is thermally cycled.
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公开(公告)号：AT143529T
公开(公告)日：1996-10-15
申请号：AT93201907
申请日：1993-07-01
Applicant: IBM
IPC: H01L21/52 , H01L21/56 , H01L21/60 , H01L23/12 , H01L23/28 , H01L23/29 , H01L23/31 , H01L23/50 , H01L21/58
Abstract: A chip carrier is disclosed which includes a chip carrier substrate and at least one semiconductor chip mounted in a flip chip configuration, via solder balls, on a circuitized surface of the chip carrier substrate. The solder balls are encapsulated in a first encapsulant having a composition which includes an epoxy. In addition, at least a portion of the circuitry on the circuitized surface is encapsulated in a second encapsulant having a composition which includes a urethane, and which composition is chosen so that the second encapsulant exhibits a modulus of elasticity which is equal to or less than about 69.10 N/m . As a consequence, the second encapsulant exhibits neither internal cracks, nor interfacial cracks at the interface with the first encapsulant, nor does the second encapsulant delaminate from the circuitized surface, when the chip carrier is thermally cycled.
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公开(公告)号：CA2091910C
公开(公告)日：1996-07-30
申请号：CA2091910
申请日：1993-03-18
Applicant: IBM
IPC: H01L21/52 , H01L21/56 , H01L21/60 , H01L23/12 , H01L23/28 , H01L23/29 , H01L23/31 , H01L23/50 , H01L23/498
Abstract: A chip carrier is disclosed which includes a chip carrier substrate and at least one semiconductor chip mounted in a flip chip configuration, via solder balls, on a circuitized surface of the chip carrier substrate. The solder balls are encapsulated in a first encapsulant having a composition which includes an epoxy. In addition, at least a portion of the circuitry on the circuitized surface is encapsulated in a second encapsulant having a composition which includes a urethane, and which composition is chosen so that the second encapsulant exhibits a modulus of elasticity which is equal to or less than about 10,000 psi. As a consequence, the second encapsulant exhibits neither internal cracks, nor interfacial cracks at the interface with the first encapsulant, nor does the second encapsulant delaminate from the circuitized surface, when the chip carrier is thermally cycled.
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公开(公告)号：MY127468A
公开(公告)日：2006-12-29
申请号：MYPI9706030
申请日：1997-12-12
Applicant: IBM
Inventor： MACQUARRIE STEPHEN WESLEY , STORR WAYNE RUSSELL , WILSON JAMES WARREN
IPC: H01L21/60 , H01L23/34 , H01L21/58 , H01L21/70 , H01L23/00 , H01L23/053 , H01L23/12 , H01L23/14 , H01L23/28 , H01L23/32 , H01L23/36 , H01L23/495 , H01L27/00 , H01L27/12 , H05K3/34
Abstract: A PACKAGE FOR MOUNTING AN INTEGRATED CIRCUIT CHIP (30, 52) TO A CIRCUIT BOARD (48) OR THE LIKE IS PROVIDED. THE PACKAGE INCLUDES A CHIP CARRIER (10) WHICH HAS A METAL SUBSTRATE (12) INCLUDING FIRST AND SECOND OPPOSED FACES. A DIELECTRIC COATING (20) IS PROVIDED ON AT LEAST ONE OF THE FACES, WHICH PREFERABLY IS LESS THAN ABOUT 20 MICRONS IN THICKNESS, AND PREFERABLY HAS A DIELECTRIC CONSTANT FROM ABOUT 35 TO ABOUT 4.0. ELECTRICAL CIRCUITRY IS DISPOSED ON THE DIELECTRIC COATING, SAID CIRCUITRY INCLUDING CHIP MOUNTING PADS (22), CONNECTION PADS (24) AND CIRCUIT TRACES (26) CONNECTING THE CHIP MOUNTING PADS TO THE CONNECTION PADS. AN IC CHIP IS MOUNTED BY FLIP CHIP OR WIRE BONDING OR ADHESIVE CONNECTION ON THE FACE OF THE METAL SUBSTRATE WHICH HAS THE DIELECTRIC COATING THEREON. IN ANY CASE, THE IC CHIP IS ELECTRICALLY CONNECTED TO THE CHIP MOUNTING PADS EITHER BY THE SOLDER BALL (54) OR WIRE BOND (36) CONNECTIONS. ELECTRICAL LEADS (38, 60) EXTEND FROM THE CONNECTION PADS ON THE CHIP CARRIER AND ARE CONNECTED TO CORRESPONDING PADS ON A CIRCUIT BOARD OR THE LIKE TO PROVIDE I/O SIGNALS FOR THE IC CHIP. IN CERTAIN EMBODIMENTS, ADDITIONAL HEAT SINKS (62) CAN BE ATTACHED TO THE CHIP CARRIER AND, ALSO IN CERTAIN EMBODIMENTS, CHIPS CAN BE MOUNTED ON BOTH SIDES OF THE CHIP CARRIER TO INCREASE THE CAPACITY OF THE CHIP CARRIER. (FIG. 1)
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Patent Agency Ranking
公开(公告)号：MY115175A
公开(公告)日：2003-04-30
申请号：MYPI9501523
申请日：1995-06-09
Applicant: IBM
Inventor： WILSON JAMES WARREN
IPC: H01L23/06 , H01L23/12 , H01L23/10 , H01L23/31 , H01L23/36 , H01L23/367 , H01L23/373 , H05K1/02 , H05K3/28 , H05K3/42
Abstract: A SEMICONDUCTOR CHIP PACKAGE AND METHOD OF MAKING SAME WHEREIN THE PACKAGE COMPRISES A CERAMIC SUBSTRATE (10) HAVING TWO LAYERS (17, 19) OF THERMALLY AND ELECTRICALLY CONDUCTIVE MATERIAL (E.G., COPPER) ON OPPOSING SURFACES THEREOF, THESE LAYERS THERMALLY AND ELECTRICALLY COUPLED BY METAL MATERIAL LOCATED WITHIN HOLES (11) PROVIDED IN THE CERAMIC. A SEMICONDUCTOR CHIP (41) IS MOUNTED ON ONE OF THESE LAYERS AND THE CONTACT SITES THEREOF ELECTRICALLY COUPLED TO SPACED CIRCUITRY (23) WHICH, IN A PREFERRED EMBODIMENT, IS FORMED SIMULTANEOUSLY WITH BOTH THERMALLY CONDUCTIVE LAYERS. COUPLING OF THE CIRCUITRY TO AN EXTERNAL SUBSTRATE (79) (E.G., PRINTED CIRCUIT BOARD) IS PREFERABLY ACCOMPLISHED USING METALLIC SPRING CLIPS (27). THESE CLIPS ARE PREFERABLY SOLDERED IN POSITION. A PREFERRED METAL FOR BEING POSITIONED WITHIN THE HOLE(S) IS SOLDER, ONE EXAMPLE BEING 10:90 TIN:LEAD SOLDER. THE PACKAGE AS PRODUCED HEREIN MAY FURTHER INCLUDE TWO QUANTITIES OF A PROTECTIVE ENCAPSULANT MATERIAL LOCATED SUBSTANTIALLY ON THE UPPER PORTIONS THEREOF TO PROTECT THE CHIP AND CIRCUITRY. THE PREFERRED MEANS FOR COUPLING THE CHIP TO THE CIRCUITRY IS TO USE A WIRE BONDING OPERATION (FIG.8)
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公开(公告)号：SG75906A1
公开(公告)日：2000-10-24
申请号：SG1998005900
申请日：1998-12-22
Applicant: IBM
Inventor： JONES GERALD WALTER , KEESLER ROSS WILLIAM , MARKOVICH VOYA RISTA , RUDIK WILLIAM JOHN , WILSON JAMES WARREN , WILSON WILLIAM EARL
Abstract: A process of fabricating a circuitized structure is provided. The process includes the steps of providing an organic substrate having circuitry thereon; applying a dielectric film on the organic substrate; forming microvias in the dielectric film; sputtering a metal seed layer on the dielectric film and the microvias; plating a metallic layer on the metal seed layer; and forming a circuit pattern thereon.
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公开(公告)号：DE69418395T2
公开(公告)日：1999-12-16
申请号：DE69418395
申请日：1994-07-07
Applicant: IBM
Inventor： CHASE ALAN WALTER , WILSON JAMES WARREN
Abstract: A chip carrier is disclosed which includes a chip carrier substrate and at least one semiconductor chip mounted in a flip chip configuration, via solder balls, on a circuitized surface of the chip carrier substrate. The solder balls are encapsulated in a first encapsulant having a composition which includes an epoxy. In addition, at least a portion of the circuitry on the circuitized surface is encapsulated in a second encapsulant having a composition which includes a urethane, and which composition is chosen so that the second encapsulant exhibits a modulus of elasticity which is equal to or less than about 10,000 psi. As a consequence, the second encapsulant exhibits neither internal cracks, nor interfacial cracks at the interface with the first encapsulant, nor does the second encapsulant delaminate from the circuitized surface, when the chip carrier is thermally cycled.
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公开(公告)号：SG44362A1
公开(公告)日：1997-12-19
申请号：SG1995002312
申请日：1993-07-01
Applicant: IBM
IPC: H01L21/56 , H01L21/60 , H01L23/12 , H01L21/52 , H01L23/28 , H01L23/29 , H01L23/31 , H01L23/50 , H01L21/58
Abstract: A chip carrier is disclosed which includes a chip carrier substrate and at least one semiconductor chip mounted in a flip chip configuration, via solder balls, on a circuitized surface of the chip carrier substrate. The solder balls are encapsulated in a first encapsulant having a composition which includes an epoxy. In addition, at least a portion of the circuitry on the circuitized surface is encapsulated in a second encapsulant having a composition which includes a urethane, and which composition is chosen so that the second encapsulant exhibits a modulus of elasticity which is equal to or less than about 69.10 N/m . As a consequence, the second encapsulant exhibits neither internal cracks, nor interfacial cracks at the interface with the first encapsulant, nor does the second encapsulant delaminate from the circuitized surface, when the chip carrier is thermally cycled.
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公开(公告)号：DE69305012D1
公开(公告)日：1996-10-31
申请号：DE69305012
申请日：1993-07-01
Applicant: IBM
IPC: H01L21/56 , H01L21/60 , H01L23/12 , H01L23/28 , H01L21/52 , H01L23/29 , H01L23/31 , H01L23/50 , H01L21/58
Abstract: A chip carrier is disclosed which includes a chip carrier substrate and at least one semiconductor chip mounted in a flip chip configuration, via solder balls, on a circuitized surface of the chip carrier substrate. The solder balls are encapsulated in a first encapsulant having a composition which includes an epoxy. In addition, at least a portion of the circuitry on the circuitized surface is encapsulated in a second encapsulant having a composition which includes a urethane, and which composition is chosen so that the second encapsulant exhibits a modulus of elasticity which is equal to or less than about 69.10 N/m . As a consequence, the second encapsulant exhibits neither internal cracks, nor interfacial cracks at the interface with the first encapsulant, nor does the second encapsulant delaminate from the circuitized surface, when the chip carrier is thermally cycled.
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