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公开(公告)号:DE3480009D1
公开(公告)日:1989-11-09
申请号:DE3480009
申请日:1984-05-23
Applicant: IBM
Inventor: JACKSON THOMAS NELSON , KIRCHNER PETER DANIEL , PETTIT GEORGE DAVID , ROSENBERG JAMES JORDAN , WOODALL JERRY MACPHERSON , WRIGHT STEVEN LORENZ
Abstract: A silicon source for molecular beam epitaxial deposition heated by electric current through the silicon is provided wherein the silicon is configured in a plurality of filaments positioned between two broader electrical contact areas. … The figures shows such a source comprising Z-shaped silicon filaments 15, 16, 17 integrated with an extending between electrical contact headers 18, 19. A current source is connected in series with the source and causes resistance heating of the source.
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公开(公告)号:DE112018002960B4
公开(公告)日:2021-07-01
申请号:DE112018002960
申请日:2018-07-16
Applicant: IBM
Inventor: WRIGHT STEVEN LORENZ , LIU YANG
IPC: B81B1/00
Abstract: Flüssigkeits-Ausgabevorrichtung (200), die aufweist:ein erstes Substrat (210), das einen in dem ersten Substrat gebildeten Behälter (222) aufweist;eine in dem Behälter (222) aufgenommene Flüssigkeit (230);eine auf der Oberfläche des ersten Substrats angeordnete Membran (220), die eine Öffnung des Behälters (222) bedeckt;ein auf das erste Substrat (210) geklebtes zweites Substrat (209), wobei das zweite Substrat eine Behälterdichtung (206) aufweist;eine auf einer Innenfläche der Membran (220) angeordnete hydrophobe Schicht (224), wobei durch die hydrophobe Schicht (224) ein Luftpolster zwischen einer Oberfläche der Flüssigkeit und der Membran (220) gebildet ist;Elektroden, die in elektrischem Kontakt mit der Membran (220) stehen; undeine auf einer Oberfläche des Behälters (222) gegenüber der Membran (220) angeordnete hydrophile Schicht (232).
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公开(公告)号:DE112018002960T5
公开(公告)日:2020-04-02
申请号:DE112018002960
申请日:2018-07-16
Applicant: IBM
Inventor: WRIGHT STEVEN LORENZ , LIU YANG
IPC: B81B1/00
Abstract: Ausführungsformen der vorliegenden Erfindung betreffen eine Flüssigkeits-Ausgabevorrichtung. Ein nicht als Einschränkung zu verstehendes Beispiel der Vorrichtung beinhaltet ein Substrat mit einem in einer Oberfläche des Substrats gebildetem Hohlraum. Die Vorrichtung kann auch eine auf der Oberfläche des Substrats angeordnete Membran enthalten, die eine Öffnung des Hohlraums bedeckt. Die Vorrichtung kann auch eine auf der Membran angeordnete hydrophobe Schicht enthalten. Die Vorrichtung kann auch eine zwischen der Membran und dem Substrat angeordnete Dichtung enthalten, wobei die Dichtung die Öffnung des Hohlraums umgibt. Die Vorrichtung kann auch eine mit der Membran verbundene Elektrodenschicht enthalten.
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公开(公告)号:DE3686087T2
公开(公告)日:1993-03-04
申请号:DE3686087
申请日:1986-05-07
Applicant: IBM
Inventor: SOLOMON PAUL MICHAEL , WRIGHT STEVEN LORENZ
IPC: H01L29/812 , H01L21/338 , H01L21/8222 , H01L27/06 , H01L27/082 , H01L27/095 , H01L29/10 , H01L29/778 , H01L29/80 , H01L29/205 , H01L27/08
Abstract: A field effect transistor structure suitable for use in an array of such structures disposed on a common substrate (14) is formed with a source terminal (22), a drain (24) terminal, and a gate terminal (26) upon an upper surface of a semiconductor chip. The chip includes a first layer (18) and a second layer (20), the first layer being grown epitaxially upon the second layer. The first layer forms a part of the gate terminal and the second layer includes a charge conduction channel coupling the source region and the drain region. A pocket layer (16) is disposed in the second layer beneath the terminals of the transistor structure and is doped with either an donor dopant or an acceptor dopant for altering the electric field at the conduction channel to insert electrons or remove electrons therefrom so as to convert an operating mode from either an enhancement mode to a depletion mode or from a depletion mode to an enchancement mode. A substrate with a terminal on the backside thereof may be placed contiguous the bottom of said second layer, the back terminal being applied to a negative source of voltage for a transistor structure of n-channel format. The semiconductor material of the chip is a obtained from compounds of elements of the groups III and V of the periodic table.
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公开(公告)号:DE3686087D1
公开(公告)日:1992-08-27
申请号:DE3686087
申请日:1986-05-07
Applicant: IBM
Inventor: SOLOMON PAUL MICHAEL , WRIGHT STEVEN LORENZ
IPC: H01L29/812 , H01L21/338 , H01L21/8222 , H01L27/06 , H01L27/082 , H01L27/095 , H01L29/10 , H01L29/778 , H01L29/80 , H01L29/205 , H01L27/08
Abstract: A field effect transistor structure suitable for use in an array of such structures disposed on a common substrate (14) is formed with a source terminal (22), a drain (24) terminal, and a gate terminal (26) upon an upper surface of a semiconductor chip. The chip includes a first layer (18) and a second layer (20), the first layer being grown epitaxially upon the second layer. The first layer forms a part of the gate terminal and the second layer includes a charge conduction channel coupling the source region and the drain region. A pocket layer (16) is disposed in the second layer beneath the terminals of the transistor structure and is doped with either an donor dopant or an acceptor dopant for altering the electric field at the conduction channel to insert electrons or remove electrons therefrom so as to convert an operating mode from either an enhancement mode to a depletion mode or from a depletion mode to an enchancement mode. A substrate with a terminal on the backside thereof may be placed contiguous the bottom of said second layer, the back terminal being applied to a negative source of voltage for a transistor structure of n-channel format. The semiconductor material of the chip is a obtained from compounds of elements of the groups III and V of the periodic table.
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公开(公告)号:SG52936A1
公开(公告)日:1998-09-28
申请号:SG1997000884
申请日:1997-03-21
Applicant: IBM
Inventor: ALT PAUL MATTHEW , CHALCO PEDRO A , FURMAN BRUCE KENNETH , HORTON RAYMOND ROBERT , NARAYAN CHANDRASEKHAR , OWENS BENAL LEE JR , WARREN KEVIN WILSON , WRIGHT STEVEN LORENZ
IPC: G02F1/1343 , G02F1/13 , G02F1/1362 , G06F11/20 , G09F9/30 , G09G3/20 , G09G3/36 , G11C29/00 , G09G3/16
Abstract: A matrix addressed display system designed so as to enable data line (22) repair by electronic mechanisms which is efficient and low in cost and thus increases yield. Such active data line (22) repair utilizes additional data driver (36) outputs, a defect map memory (48) in the TFT/LCD module and modification of the data stream to the data drivers (36) by additional circuits (42) between the display and the display adapter. A bus configuration on the display substrate is utilized which combines repair flexibility, low parasitic capacitance, and the ability to easily make the necessary interconnections. The number of interconnections is kept to a minimum, the connections are reliable, and the connections may be made with conventional wire bond or laser bond technology, or disk bond technology.
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公开(公告)号:DE3786343T2
公开(公告)日:1994-01-20
申请号:DE3786343
申请日:1987-12-08
Applicant: IBM
Inventor: KIRCHNER PETER DANIEL , MARKS RONALD FRANKLIN , PETTIT GEORGE DAVID , WOODALL JERRY MAC PHERSON , WRIGHT STEVEN LORENZ
IPC: H01L31/0248 , H01L31/02 , H01L31/0216 , H01L31/08 , H01L31/10 , H01L33/44 , H01S5/00 , H01L21/203
Abstract: An environmental interface for a semiconductor electro-optical conversion device layer that is optically transparent, electrically conductive and chemically passivating, made of an elemental semiconductor with an indirect band gap I> 1 electron volt in a layer between 2 and 20 nm thick. A GaAs (2) covered by GaAlAs converter with a 10 nm Si layer (6) over the GaAlAs (4) is illustrated.
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公开(公告)号:DE3786343D1
公开(公告)日:1993-07-29
申请号:DE3786343
申请日:1987-12-08
Applicant: IBM
Inventor: KIRCHNER PETER DANIEL , MARKS RONALD FRANKLIN , PETTIT GEORGE DAVID , WOODALL JERRY MAC PHERSON , WRIGHT STEVEN LORENZ
IPC: H01L31/0248 , H01L31/02 , H01L31/0216 , H01L31/08 , H01L31/10 , H01L33/44 , H01S5/00 , H01L21/203
Abstract: An environmental interface for a semiconductor electro-optical conversion device layer that is optically transparent, electrically conductive and chemically passivating, made of an elemental semiconductor with an indirect band gap I> 1 electron volt in a layer between 2 and 20 nm thick. A GaAs (2) covered by GaAlAs converter with a 10 nm Si layer (6) over the GaAlAs (4) is illustrated.
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公开(公告)号:DE3783162T2
公开(公告)日:1993-07-01
申请号:DE3783162
申请日:1987-05-26
Applicant: IBM
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