公开(公告)号：JP2000031427A

公开(公告)日：2000-01-28

申请号：JP18081199

申请日：1999-06-25

Applicant: SIEMENS AG ,  IBM

Inventor： SCHREMS MARTIN ,  MANDELMAN JACK ,  HOEPFNER JOACHIM ,  SCHAEFER HERBERT ,  STENGL REINHARD

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

Abstract: PROBLEM TO BE SOLVED: To provide a trench capacitor, wherein the rough surface of a trench sidewall is suppressed. SOLUTION: In a trench capacitor 301, an epitaxial layer 365 is provided at the lower part of the trench. The epitaxial layer 365 is used as an embedded plate of the trench capacitor. Furthermore, the trench lower part is surrounded by a diffused region 367, which results in higher dopant concentration of the epitaxial layer 365. The diffused region 367 is formed through vapor-phase doping, plasma doping, or plasma infiltration ion implantation.

公开(公告)号：WO2007023011B1

公开(公告)日：2007-07-12

申请号：PCT/EP2006063581

申请日：2006-06-27

Applicant: IBM ,  IBM UK ,  MANDELMAN JACK ,  CHENG KANGGUO ,  DIVAKARUNI RAMACHANDRA ,  RADENS CARL ,  WANG GENG

Inventor： MANDELMAN JACK ,  CHENG KANGGUO ,  DIVAKARUNI RAMACHANDRA ,  RADENS CARL ,  WANG GENG

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L27/108 ,  H01L27/10829 ,  H01L27/10867 ,  H01L27/1203

Abstract: A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.

Abstract translation: 使用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储单元和工艺顺序。 具体地，本发明提供了与现有SOI CMOS技术兼容的致密的高性能SRAM单元替换。 各种增益单元布局在本领域中是已知的。 本发明通过提供利用SOI CMOS制造的致密布局来改善现有技术的状态。 通常，存储单元包括分别设置有栅极，源极和漏极的第一晶体管; 分别具有第一栅极，第二栅极，源极和漏极的第二晶体管; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。

公开(公告)号：WO2007051765A3

公开(公告)日：2007-06-28

申请号：PCT/EP2006067883

申请日：2006-10-27

Applicant: IBM ,  IBM UK ,  HSU LOUIS LU-CHEN ,  MANDELMAN JACK ,  TONTI WILLIAM

Inventor： HSU LOUIS LU-CHEN ,  MANDELMAN JACK ,  TONTI WILLIAM

IPC: H01L23/525

CPC classification number: H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electrically programmable fuse (eFuse) includes (1) a semiconducting layer above an insulating oxide layer of a substrate; (2) a diode formed in the semiconducting layer; and (3) a silicide layer formed on the diode. The diode comprises an N+,p-,P+ or P+,n-,N+ structure.

Abstract translation: 电可编程熔丝（eFuse）包括（1）衬底的绝缘氧化物层上的半导体层; （2）形成在半导体层中的二极管; 和（3）在二极管上形成的硅化物层。 二极管包括N +，p-，P +或P +，n-，N +结构。

公开(公告)号：JP2000216354A

公开(公告)日：2000-08-04

申请号：JP2000005490

申请日：2000-01-14

Applicant: IBM ,  SIEMENS AG

Inventor： MANDELMAN JACK ,  RADENS CARL ,  GRUENING ULRIKE

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming an embedded self-aligned strap in a deep storage trench. SOLUTION: A spacer 42/52 is formed on the wall face of a recess on an already filled deep trench capacitor 30. A plug 46/54 is formed within the region between spacers. A photoresist is stuck onto the spacer 42/54 and the plug 46/54 and a peripheral material 40, and a part of the plug 46/54, the spacer 42/52, and the material 40 is exposed. The spacer part not covered with the photoresist is selectively etched. A board and a trench part exposed by the removal of the spacer are selectively etched. An isolation region 58 is formed within the space made etching.

公开(公告)号：JP2000196045A

公开(公告)日：2000-07-14

申请号：JP37569999

申请日：1999-12-28

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： RADENS CARL ,  GRUENING ULRIKE ,  DEBROSSE JOHN ,  MANDELMAN JACK

IPC: H01L29/78 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To obtain necessary insulation between a capacitor for storage and a transistor in a memory cell, using both a capacitor for storage in a vertical trench and a vertical transistor. SOLUTION: One memory cell formed in a semiconductor main body 10 includes a polycrystalline silicon packing part 22 as a capacitor for storage and one field-effect transistor. This field-effect transistor includes a source 43 formed in the sidewall of a trench, a drain 42 formed in the semiconductor main body and provided with a surface in common with the upper face of the semiconductor main body, a channel region including both vertical and horizontal parts, and a polycrystalline silicon gate at the upper part of the trench. Thus, an insulating oxide layer 28 at the top end of the polycrystalline silicon packing part, which is useful as a storage node and the polycrystalline silicon packing part which is useful as a gate conductor can be obtained in this process for manufacturing.

公开(公告)号：WO0245130A3

公开(公告)日：2004-01-08

申请号：PCT/US0144625

申请日：2001-11-28

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： GRUENING ULRIKE ,  DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK ,  RUPP THOMAS

IPC: H01L27/10 ,  H01L21/8242

CPC classification number: H01L27/10894 ,  H01L27/10864 ,  H01L27/10885 ,  H01L27/10891

Abstract: A process for producing very high-density embedded DRAM/very high-performance logic structures comprising fabricating vertical MOSFET DRAM cells with salicided source/drain and gate conductor dual workfunction MOSFETs in the supports, comprising: Forming a french capacitor in a silicon substrate having a gate oxide layer, a polysilicon layer, and a top dialectric nitride layer deposited thereon; Applying a patterned mask over the array and support areas and forming recesses in the nitride layer, the polysilicon layer, and shallow trench isolation region; Forming a silicide and oxide cap in the recesses in the nitride layer, the polysilicon layer, and shallow trench isolation region; Applying a block mask to protect the supports while stripping the nitride layer from the array and etching the exposed polysilicon layer to the top of the gate oxide layer; Striping the nitride layer from the support region and depositing a polysilicon layer over the array and support areas; Applying a mask to pattern and form a bitline diffusion stud landing pad in the array and gate conductors for the support transistors; Saliciding the tops of the landing pad and the gate conductors; Applying an interlevel oxide layer and then opening vias in the interlevel oxide layer for establishing conductive wiring channels.

Abstract translation: 一种用于生产非常高密度的嵌入式DRAM /非常高性能的逻辑结构的方法，包括在支撑体中制造具有水银源/漏极和栅极导体双功函数MOSFET的垂直MOSFET DRAM单元，包括：在硅衬底中形成法兰电容器， 栅极氧化物层，多晶硅层和沉积在其上的顶部侧面氮化物层; 在阵列和支撑区域上施加图案化掩模并在氮化物层，多晶硅层和浅沟槽隔离区域中形成凹陷; 在氮化物层，多晶硅层和浅沟槽隔离区域的凹槽中形成硅化物和氧化物盖; 施加阻挡掩模以保护支撑物，同时从阵列剥离氮化物层并将暴露的多晶硅层蚀刻到栅极氧化物层的顶部; 从支撑区域剥离氮化物层并在阵列和支撑区域上沉积多晶硅层; 应用掩模来图案化并在阵列中形成位线扩散螺柱着陆焊盘，并在支撑晶体管上形成栅极导体; 打击着陆板和门导体的顶部; 施加层间氧化层，然后在层间氧化层中开通通孔，以建立导电布线通道。

公开(公告)号：CZ295847B6

公开(公告)日：2005-11-16

申请号：CZ20011964

申请日：1999-11-26

Applicant: IBM

Inventor： AGAHI FARID ,  HSU LOUIS ,  MANDELMAN JACK

IPC: H01L21/8242 ,  H01L27/108

Abstract: In the present invention, there is disclosed a memory device (200) in a substrate having a trench with side walls in the substrate, said memory device (200) including bit line conductors (246) and word line conductors (230). Signal storage node has a first electrode (202), a second electrode (204) formed within the trench (252; DT), and a node dielectric (206) formed between the electrodes (202, 204). The signal transfer device has: an annular signal transfer region (222) with outer surface adjacent side walls (212) of the trench (252; DT), an inner surface, a first and a second end; a first diffusion region (218) coupling the first end of the signal transfer region (222) to the second electrode (204) of the signal storage node; a second diffusion region (220) coupling the second end of signal transfer region (222) to the bit line conductor (246); a gate insulator (224) coating the inner surface of signal transfer region (222); and a gate conductor (226) coating the gate insulator (224) and coupled to the word line conductor (230). A conductive connecting member (236) couples the signal transfer region (222) to a reference voltage.

公开(公告)号：WO2006110781A3

公开(公告)日：2007-04-19

申请号：PCT/US2006013561

申请日：2006-04-12

Applicant: IBM ,  MANDELMAN JACK ,  HO HERBERT ,  NING TAK ,  OTANI YOICHI

Inventor： MANDELMAN JACK ,  HO HERBERT ,  NING TAK ,  OTANI YOICHI

IPC: H01L29/76

CPC classification number: H01L27/115 ,  G11C16/0466 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/792 ,  H01L29/7926

Abstract: The present invention provides two-transistor silicon-oxide-nitride-oxide-semiconductor (2-Tr SONOS) non-volatile memory cells with randomly accessible storage locations as well as method of fabricating the same, hi one embodiment, a 2-Tr SONOS cell is provided in which the select transistor is located within a trench structure having trench depth from 1 to 2 µm and the memory transistor is located on a surface of a semiconductor substrate adjoining the trench structure. In another embodiment, a 2-Tr SONOS memory cell is provided in which both the select transistor and the memory transistor are located within a trench structure having the depth mentioned above.

Abstract translation: 本发明提供了具有随机访问的存储位置的双晶体管氧化硅 - 氧化物 - 氧化物半导体（2-Tr SONOS）非易失性存储单元及其制造方法。在一个实施例中，2-Tr SONOS 提供了选择晶体管位于具有1至2μm的沟槽深度的沟槽结构内的单元，并且存储晶体管位于与沟槽结构相邻的半导体衬底的表面上。 在另一个实施例中，提供了2-Tr SONOS存储单元，其中选择晶体管和存储晶体管都位于具有上述深度的沟槽结构内。

公开(公告)号：WO03025977A3

公开(公告)日：2003-08-14

申请号：PCT/US0230369

申请日：2002-09-17

Applicant: IBM

Inventor： PARK BYEONGJU ,  FURUKAWA TOSHIHARU ,  MANDELMAN JACK

IPC: H01L29/41 ,  H01L21/336 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/785 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78618

Abstract: The present invention relates to a wrapped-gate transistor including a substrate having an upper surface and first and second side surfaces opposing to each other. Source and drain regions (28) are formed in the substrate with a channel region therebetween. The channel region extends from the first side surface to the second side surfaces of the substrate. A gate dielectric layer (40) is formed on the substrate. A gate electrode (42) is formed on the gate dielectric layer (40) to cover the channel region from the upper surface and the first and second side surfaces with the gate dielectric (40) therebetween. The substrate is a silicon island (12) formed on an insulation layer of an SOI (silicon-on-insulator) substrate or a conventional non-SOI substrate, and has four side surfaces including the first and second side surfaces. The source and drain regions (28) are formed on the portions of the substrate adjoining the third and fourth side surfaces which are perpendicular to the first and second side surfaces. The wrapped-gate structure provides a better and quicker potential control within the channel area, which yields steep sub-threshold slope and low sensitivity to the "body-to-source" voltage.

Abstract translation: 本发明涉及包括具有上表面和彼此相对的第一和第二侧表面的衬底的缠绕栅极晶体管。 源极和漏极区域（28）形成在衬底中，其间具有沟道区域。 沟道区域从衬底的第一侧表面延伸到第二侧表面。 栅极电介质层（40）形成在衬底上。 栅极电极（42）形成在栅极电介质层（40）上，以从上表面和第一和第二侧表面覆盖沟道区域，栅电介质（40）位于它们之间。 衬底是形成在SOI（绝缘体上硅）衬底或常规非SOI衬底的绝缘层上的硅岛（12），并且具有包括第一和第二侧表面的四个侧表面。 源极和漏极区域（28）形成在与第一和第二侧表面垂直的第三和第四侧表面相邻的基板的部分上。 包封门结构在通道区域内提供了更好更快的电位控制，从而产生陡峭的次阈值斜率和对“体对电压”电压的低灵敏度。

公开(公告)号：WO0231878A3

公开(公告)日：2002-10-31

申请号：PCT/US0126644

申请日：2001-08-24

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： JAIPRAKASH VENKATACHALAN ,  MANDELMAN JACK ,  DIVAKARUNI RAMACHANDRAR ,  MALIK RAJEEV ,  SEITZ MIHEL

IPC: H01L21/8242

CPC classification number: H01L27/10861

Abstract: An array top oxide is protected in the manufacture of vertical metal oxide semiconductor field effect transistor (MOSFET) dynamic random access memory (DRAM) arrays by a protective etch stop layer (18) which protects the top oxide (16) and prevents word line to substrate shorts and/or leakage. Processing of a DRAM device containing vertical MOSFET arrays proceeds through planarization of the array gate conductor polysilicon (17) of the vertical MOSFET to the top surface of the top oxide (16). A thin polysilicon layer (18) is deposited over the planarized surface and an active area (AA) pad nitride and tetraethyl orthosilicate (TEOS) stack is deposited. The AA mask is used to open the pad layer to the silicon surface, and shallow trench isolation (STI) etching is used to form isolation trenches (20).

Abstract translation: 在通过保护顶部氧化物（16）的保护性蚀刻停止层（18）制造垂直金属氧化物半导体场效应晶体管（MOSFET）动态随机存取存储器（DRAM）阵列中的阵列顶部氧化物被保护，并且防止字线 衬底短路和/或泄漏。 包括垂直MOSFET阵列的DRAM器件的处理通过将垂直MOSFET的阵列栅极导体多晶硅（17）平坦化到顶部氧化物（16）的顶表面进行。 在平坦化表面上沉积薄多晶硅层（18），并沉积有源区（AA）衬垫氮化物和原硅酸四乙酯（TEOS）堆叠。 使用AA掩模将焊盘层打开到硅表面，并且使用浅沟槽隔离（STI）蚀刻来形成隔离沟槽（20）。