公开(公告)号：DE10348641A1

公开(公告)日：2005-05-25

申请号：DE10348641

申请日：2003-10-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HELNEDER JOHANN ,  SCHWERD MARKUS ,  GOEBEL THOMAS ,  MITCHELL ANDREA ,  KOERNER HEINRICH ,  DREXL STEFAN ,  SECK MARTIN

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/76 ,  H01L27/08

公开(公告)号：DE10314511A1

公开(公告)日：2003-11-13

申请号：DE10314511

申请日：2003-03-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOEBEL THOMAS ,  ROBL WERNER ,  WRSCHKA PETER

IPC: H01L21/3105 ,  H01L21/768 ,  H01L21/302

Abstract: In a method of planarizing a semiconductor wafer, the improvement comprising polishing above metal interconnect lines to uniformly polish the topography of the wafer to a predetermined endpoint on the wafer sufficiently close above the metal interconnect lines, yet far enough away from the lines to prevent damage to the lines, comprising: a) filling gaps between metal interconnect lines of an inter metal dielectric in a wafer being formed, by depositing HDP fill on top of the metal interconnects, between the metal interconnects, and on the surface of a substrate or dielectric layer between the metal interconnects to create an HDP overfill so that the level of the bottom of roofs of the overfill above the metal lines is the endpoint upon use of FAP to remove topography; d) contacting the surface of HDP overfill of the processed semiconductor wafer from step a) with a fixed abrasive polishing pad; and e) relatively moving the wafer and the fixed abrasive polishing pad to affect a polishing rate sufficient to reach the predetermined endpoint and uniformly planar surface on the wafer sufficiently close above the metal interconnect lines and yet far enough away from the lines to prevent damage to the lines.

公开(公告)号：DE10341059A1

公开(公告)日：2005-04-14

申请号：DE10341059

申请日：2003-09-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HELNEDER JOHANN ,  SCHWERD MARKUS ,  GOEBEL THOMAS ,  MITCHELL ANDREA ,  KOERNER HEINRICH ,  SECK MARTIN ,  TORWESTEN HOLGER

IPC: H01L21/02 ,  H01L21/316 ,  H01L23/522 ,  H01L27/01 ,  H01L27/08 ,  H01L21/822 ,  H01G9/042

Abstract: An integrated circuit and fabrication method are presented. The integrated circuit includes a capacitor containing a base electrode, a covering electrode, and a dielectric between the base and covering electrodes. The dielectric contains an oxide of a material contained in the base electrode, which may be produced by anodic oxidation. A peripheral edge of the dielectric is uncovered by the covering electrode. A base layer on the capacitor includes a cutout adjacent to the dielectric. During fabrication, the base layer protects the material of the base electrode that is to be anodically oxidized from chemicals, and also protects the surrounding regions from anodic oxidation. A precision resistor may be fabricated simultaneously with the capacitor.