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    3.
    发明专利
    未知

    公开(公告)号：DE10341059B4

    公开(公告)日：2007-05-31

    申请号：DE10341059

    申请日：2003-09-05

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HELNEDER JOHANN ,  SCHWERD MARKUS ,  GOEBEL THOMAS ,  MITCHELL ANDREA ,  KOERNER HEINRICH ,  SECK MARTIN ,  TORWESTEN HOLGER

    IPC: H01L27/08 ,  H01G9/042 ,  H01L21/02 ,  H01L21/316 ,  H01L21/822 ,  H01L23/522 ,  H01L27/01 ,  H01L27/06

    Abstract: An integrated circuit and fabrication method are presented. The integrated circuit includes a capacitor containing a base electrode, a covering electrode, and a dielectric between the base and covering electrodes. The dielectric contains an oxide of a material contained in the base electrode, which may be produced by anodic oxidation. A peripheral edge of the dielectric is uncovered by the covering electrode. A base layer on the capacitor includes a cutout adjacent to the dielectric. During fabrication, the base layer protects the material of the base electrode that is to be anodically oxidized from chemicals, and also protects the surrounding regions from anodic oxidation. A precision resistor may be fabricated simultaneously with the capacitor.

    8.
    发明专利
    未知

    公开(公告)号：DE10337569A1

    公开(公告)日：2005-03-24

    申请号：DE10337569

    申请日：2003-08-14

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HELNEDER JOHANN ,  GOEBEL THOMAS ,  SCHWERD MARKUS ,  MITCHELL ANDREA ,  KOERNER HEINRICH ,  SECK MARTIN ,  DREXL STEFAN ,  KLEIN WOLFGANG ,  HOMMEL MARTINA

    IPC: H01L23/485 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768

    Abstract: A connection arrangement having an outer conductive structure arranged at least partly or completely in a cutout of an electrical insulation layer is provided. An inner conductive structure is arranged at the bottom of the cutout on one side of the insulation layer. The inner conductive structure adjoins the outer conductive structure in a contact zone. A contact area is arranged at the outer conductive structure on the other side of the cutout. The contact zone and the contact area do not overlap. The bottom of the cutout is arranged to overlaps at least half of the contact area, to provide a step in the insulation layer at the edge of the cutout outside a main current path between the contact area and the inner conductive structure.

    9.
    发明专利
    未知

    公开(公告)号：DE10354937A1

    公开(公告)日：2004-06-17

    申请号：DE10354937

    申请日：2003-11-25

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ROBL WERNER ,  SEITZ MIHEL ,  GOEBEL THOMAS ,  MALIK RAJEEV

    IPC: H01L21/768 ,  H01L21/8242 ,  H01L21/285

    Abstract: A method of forming a semiconductor device includes providing a semiconductor device including a conductor formed thereon. A dielectric layer is formed over the conductor and a recess is formed in the dielectric layer by removing a portion of the dielectric layer to expose at least a portion of the conductor. A first layer of aluminum is deposited over the top surface of the dielectric, along the sidewalls of the dielectric layer and over the exposed portion of the conductor without altering the temperature of the semiconductor device. A second layer of aluminum is deposited over the first layer of aluminum at a temperature greater than about 300° C. A third layer of aluminum is deposited over the second layer of aluminum so as to completely fill the recess in the dielectric layer. The third layer of aluminum is slow deposited at a temperature greater than about 300° C.

    10.
    发明专利
    未知

    公开(公告)号：DE10311368A1

    公开(公告)日：2003-11-20

    申请号：DE10311368

    申请日：2003-03-14

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ROBL WERNER ,  BRINTZINGER AXEL ,  FRIESE GERALD ,  GOEBEL THOMAS

    IPC: H01L21/60 ,  H01L23/31 ,  H01L23/485 ,  H01L21/28

    Abstract: Disclosed is a method of ball grid array packaging, comprising the steps of providing a semiconductor die having a metal conductors thereon, covering said metal conductors with an insulative layer, etching through said insulative layer so as to provide one or more openings to said metal conductors, depositing a compliant material layer, etching through said compliant material layer so as to provide one or more openings to said metal conductors, depositing a substantially homogenous conductive layer, patterning said conductive layer so as to bring at least one of said metal conductors in electrical contact with one or more pads, each said pad comprising a portion of said conductive layer disposed upon said compliant material, and providing solder balls disposed upon said pads. Also disclosed is the apparatus made from the method.

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