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    ARCHITECTURE FOR HIGH-SPEED MAGNETIC MEMORIES
    11.
    发明申请
    ARCHITECTURE FOR HIGH-SPEED MAGNETIC MEMORIES 审中-公开
    高速磁记忆体的结构

    公开(公告)号：WO2004055821A3

    公开(公告)日：2004-11-04

    申请号：PCT/EP0314011

    申请日：2003-12-10

    Applicant: INFINEON TECHNOLOGIES AG ,  IBM

    Inventor： GOGL DIETMAR ,  SCHEUERLEIN ROY EDWIN ,  REOHR WILLIAM ROBERT

    IPC: G11C11/16

    CPC classification number: G11C11/1693 ,  G11C11/1673 ,  G11C11/1675

    Abstract: A magnetic memory circuit comprises a plurality of memory cells and a plurality of bit lines coupled to the memory cells for selectively accessing one or more of the memory cells. The memory circuit comprises at least one bit line programming circuit, configurable as a current source for generating a programming current for writing a logical state of at least one memory cell and/or a current sink for returning the programming current, and a first set of switches. The first set of switches are disabled at least during a read operation of the memory cells and at least a portion of the first set of switches are selectively enabled during a write operation of the memory cells. Each switch in the first set of switches is configured to selectively couple the at least one bit line programming circuit to a corresponding one of the bit lines in response to a first control signal. The memory circuit further comprises at least one sense amplifier and a second set of switches. The second set of switches are disabled at least during a write operation of the memory cells and at least a portion of the second set of switches are selectively enabled during a read operation of the memory cells. Each switch in the second set of switches is configured to selectively couple the at least one sense amplifier to a corresponding one of the bit lines in response to a second control signal.

    Abstract translation: 磁存储器电路包括多个存储器单元和耦合到存储器单元的多个位线，用于选择性地访问一个或多个存储器单元。 存储器电路包括至少一个位线编程电路，可配置为用于产生用于写入至少一个存储器单元的逻辑状态的编程电流的电流源和/或用于返回编程电流的电流吸收器，以及第一组 开关。 至少在存储器单元的读取操作期间禁用第一组开关，并且在存储器单元的写入操作期间选择性地使能第一组开关的至少一部分。 第一组开关中的每个开关被配置为响应于第一控制信号选择性地将至少一个位线编程电路耦合到对应的位线。 存储器电路还包括至少一个读出放大器和第二组开关。 至少在存储器单元的写入操作期间禁用第二组开关，并且在存储器单元的读取操作期间，第二组开关的至少一部分被选择性地使能。 第二组开关中的每个开关被配置为响应于第二控制信号选择性地将至少一个读出放大器耦合到对应的一个位线。

    16.
    发明专利
    未知

    公开(公告)号：DE102005053717A1

    公开(公告)日：2006-07-06

    申请号：DE102005053717

    申请日：2005-11-10

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GOGL DIETMAR ,  VIEHMANN HANS-HEINRICH

    IPC: G11C11/15 ,  G11C7/06

    Abstract: A current sense amplifier including clamping devices and a current mirror is configured to sense the resistance of an MTJ memory cell utilizing a bitline boost circuit to shorten the charging time for parasitic circuit capacitance. The bitline boost circuit includes a source follower coupled to a reference voltage and a switch coupled to another voltage source. The switch is enabled to conduct during an initial period of sensing the resistance of the memory cell. The source follower in the bitline boost circuit is configured to clamp the voltage of an input signal at substantially the same level as the clamping devices, and to provide additional current to shorten the period for charging parasitic capacitance. The resulting current sense amplifier can be used to implement a memory device with fast and reliable read times and low manufacturing cost.

    ARCHITECTURE FOR HIGH-SPEED MAGNETIC MEMORIES
    17.
    发明专利
    ARCHITECTURE FOR HIGH-SPEED MAGNETIC MEMORIES 未知

    公开(公告)号：AU2003293828A1

    公开(公告)日：2004-07-09

    申请号：AU2003293828

    申请日：2003-12-10

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GOGL DIETMAR ,  SCHEUERLEIN ROY EDWIN ,  REOHR WILLIAM ROBERT

    IPC: G11C11/16

    Abstract: A magnetic memory circuit comprises a plurality of memory cells and a plurality of bit lines coupled to the memory cells for selectively accessing one or more of the memory cells. The memory circuit comprises at least one bit line programming circuit, configurable as a current source for generating a programming current for writing a logical state of at least one memory cell and/or a current sink for returning the programming current, and a first set of switches. The first set of switches are disabled at least during a read operation of the memory cells and at least a portion of the first set of switches are selectively enabled during a write operation of the memory cells. Each switch in the first set of switches is configured to selectively couple the at least one bit line programming circuit to a corresponding one of the bit lines in response to a first control signal. The memory circuit further comprises at least one sense amplifier and a second set of switches. The second set of switches are disabled at least during a write operation of the memory cells and at least a portion of the second set of switches are selectively enabled during a read operation of the memory cells. Each switch in the second set of switches is configured to selectively couple the at least one sense amplifier to a corresponding one of the bit lines in response to a second control signal.

    18.
    发明专利
    未知

    公开(公告)号：DE10112281A1

    公开(公告)日：2002-09-26

    申请号：DE10112281

    申请日：2001-03-14

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GOGL DIETMAR ,  VIEHMANN HANS-HEINRICH

    IPC: G11C11/15 ,  G11C7/06

    Abstract: A memory sense amplifier (10) for a semiconductor memory device (1) is provided with a compensation current source device (30) which generates a compensation current (Icomp) and feeds it to an interconnected bit line (4). Said compensation current (Icomp) is selected in such a manner that during readout a potential gradient can be generated and/or maintained in cooperation with a compensation voltage source device (20) on the selected and interlinked bit line device (4) that is substantially constant over time.

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