公开(公告)号：DE102004044686A1

公开(公告)日：2006-03-16

申请号：DE102004044686

申请日：2004-09-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOLLER KLAUS ,  KRIZ JAKOB

IPC: H01L23/522 ,  H01L21/768

Abstract: An integrated circuit arrangement containing a via is disclosed. The via has an upper section having greatly inclined sidewalls. A lower section of the via has approximately vertical sidewalls. In one embodiment, a liner layer is used as a hard mask in the production of the via and defines the position of the sections of the via.

公开(公告)号：DE102004029519A1

公开(公告)日：2006-01-12

申请号：DE102004029519

申请日：2004-06-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WENDT HERMANN ,  GOLLER KLAUS

IPC: H01L21/768

Abstract: The invention relates to a method for producing a layer arrangement. An electrically conductive layer is formed and patterned. A sacrificial layer formed on at least part of the patterned electrically conductive layer. An electrically insulating layer is formed on the electrically conductive and sacrificial layers and is patterned in such a manner that one or more surface areas of the sacrificial layer are exposed. The exposed areas of the sacrificial layer are removed to expose one or more surface areas of the patterned electrically conductive layer. The patterned electrically conductive layer is covered with a pattern of electrically conductive material.

公开(公告)号：DE102004014676A1

公开(公告)日：2005-10-20

申请号：DE102004014676

申请日：2004-03-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HEITZSCH OLAF ,  GOLLER KLAUS ,  NICHTERWITZ MARION

IPC: G03F9/00 ,  H01L23/544

公开(公告)号：DE10305365A1

公开(公告)日：2004-08-26

申请号：DE10305365

申请日：2003-02-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHWALBE GRIT ,  GOLLER KLAUS ,  REB ALEXANDER

IPC: H01L21/768 ,  H01L23/485 ,  H01L21/283 ,  H01L21/336 ,  H01L21/331

Abstract: A contact hole is provided in an insulating layer over a substrate surface. The contact hole is filled with a conductive material and a second insulating layer is provided on the first insulating layer and the filled contact hole. An etching mask is used to etch a first recess to expose the conductive material filling the contact hole, and a second recess through the two insulating layers to expose a connection surface. A conductive material is placed in the two recesses to form two contact terminals. An independent claim is included for a device for contacting substrate connections.

公开(公告)号：DE10260352A1

公开(公告)日：2004-07-15

申请号：DE10260352

申请日：2002-12-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOLLER KLAUS ,  FOESTE BERND ,  KRIZ JAKOB ,  BACHMANN JENS

IPC: H01L27/08 ,  H01L21/822 ,  H01L21/768

Abstract: To make the capacitor arrangement (110) a stack (124b) of the following layers is produced: a base electrode layer (14), a base dielectric layer (16), at least one central electrode layer (18), a dielectric layer covering (20) and an electrode layer covering (22). This layer (22) and the central electrode layer (18) are structured in the first lithographic process. The electrode layer covering (22a) and the base electrode layer (14) are structured using a second lithographic process. An independent claim is included for the corresponding integrated capacitor arrangement.

公开(公告)号：DE10247486A1

公开(公告)日：2004-04-22

申请号：DE10247486

申请日：2002-10-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOLLER KLAUS ,  MUELLER MARC ,  WENZEL ROLAND

IPC: H01L23/544 ,  H01L21/66

Abstract: A test structure to give process exactness in the production of aligned structures on substrates comprises two test patterns (801,803) produced using two masks which have four overlapping sections (8011-8014,8031-8034) which allow process displacement in four different directions. An Independent claim is also included for a process to produce exact alignment as above.

公开(公告)号：DE10326087B4

公开(公告)日：2008-03-20

申请号：DE10326087

申请日：2003-06-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOLLER KLAUS ,  GRUENEBERG DIRK ,  BACHMANN JENS ,  SCHWAB REINER

IPC: H01L27/06 ,  H01L21/30 ,  H01L21/3213 ,  H01L21/70 ,  H01L27/08

Abstract: Component comprises an active structure (814) arranged on a substrate (800) and having side walls (818), and an auxiliary structure (100) arranged next to the active structure on the substrate and having side edges (102). The side edges of the active structure lie opposite the side edges of the auxiliary structure by a distance. The auxiliary structure-active structure distance is dimensioned so that one shape of the active structure side edges or one shape of the substrate next to the active structure side edges are different from the shape of the component in which the auxiliary structure is not present. An independent claim is also included for a process for the production of a component.

公开(公告)号：DE102004044686B4

公开(公告)日：2006-08-31

申请号：DE102004044686

申请日：2004-09-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOLLER KLAUS ,  KRIZ JAKOB

IPC: H01L23/522 ,  H01L21/768

Abstract: An integrated circuit arrangement containing a via is disclosed. The via has an upper section having greatly inclined sidewalls. A lower section of the via has approximately vertical sidewalls. In one embodiment, a liner layer is used as a hard mask in the production of the via and defines the position of the sections of the via.

公开(公告)号：DE102004029519A9

公开(公告)日：2006-05-11

申请号：DE102004029519

申请日：2004-06-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WENDT HERMANN ,  GOLLER KLAUS

IPC: H01L21/768

Abstract: The invention relates to a method for producing a layer arrangement. An electrically conductive layer is formed and patterned. A sacrificial layer formed on at least part of the patterned electrically conductive layer. An electrically insulating layer is formed on the electrically conductive and sacrificial layers and is patterned in such a manner that one or more surface areas of the sacrificial layer are exposed. The exposed areas of the sacrificial layer are removed to expose one or more surface areas of the patterned electrically conductive layer. The patterned electrically conductive layer is covered with a pattern of electrically conductive material.

公开(公告)号：DE10344605A1

公开(公告)日：2005-05-04

申请号：DE10344605

申请日：2003-09-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WENZEL ROLAND ,  GOLLER KLAUS

IPC: H01L23/522 ,  H01L23/528

Abstract: An interconnect connection structure having first and second interconnects and multiple connection elements that electrically connect the first interconnect to the second interconnect is described. The multiple connection elements are formed laterally in a lateral region of the first and second interconnects relative to an overlay orientation of the interconnects. A central region may be free of connection elements so that electro-migration properties of the connection structure are improved and the current-carrying capacity is increased.