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    SEMICONDUCTOR STRUCTURE AND METHOD FOR THE PRODUCTION THEREOF
    1.
    发明申请
    SEMICONDUCTOR STRUCTURE AND METHOD FOR THE PRODUCTION THEREOF 审中-公开
    半导体结构及其制造方法

    公开(公告)号：WO03038893A2

    公开(公告)日：2003-05-08

    申请号：PCT/EP0211853

    申请日：2002-10-23

    Applicant: INFINEON TECHNOLOGIES AG ,  GRATZ ACHIM ,  KRIZ JAKOB

    Inventor： GRATZ ACHIM ,  KRIZ JAKOB

    IPC: H01L21/8249 ,  H01L27/06

    CPC classification number: H01L27/0623 ,  H01L21/8249

    Abstract: The invention relates to a semiconductor structure and to a method for the production thereof, wherein a substrate (210) is provided with a first main surface and a recess (220) is made in the main surface of the substrate (210). An active area (244, 24, 250) of the conductor structure is created in the region of the bottom of the recess (220) and contact areas (252) of at least one part of the connections are made in the direction of the first surface of the substrate (210).

    Abstract translation: 本发明提供一种半导体结构及其制造方法，其中在具有第一主表面的衬底（210）上的衬底（210）的第一主表面中形成凹槽（220）。 此外，半导体结构的有源区域（244,246,250）在凹槽（220）底部的区域中产生，并且端子的至少一部分的引出区域（252）沿基板（210）的第一表面的方向引出。

    METHOD FOR PRODUCING A BIPOLAR TRANSISTOR COMPRISING A POLYSILICON EMITTER
    2.
    发明申请
    METHOD FOR PRODUCING A BIPOLAR TRANSISTOR COMPRISING A POLYSILICON EMITTER 审中-公开
    用于生产双极型多晶硅发射

    公开(公告)号：WO03007361A3

    公开(公告)日：2003-04-24

    申请号：PCT/EP0208234

    申请日：2002-07-10

    Applicant: INFINEON TECHNOLOGIES AG ,  KRIZ JAKOB ,  SECK MARTIN ,  TILKE ARMIN

    Inventor： KRIZ JAKOB ,  SECK MARTIN ,  TILKE ARMIN

    IPC: H01L21/225 ,  H01L21/331 ,  H01L29/737

    CPC classification number: H01L29/66272 ,  H01L21/2257

    Abstract: The invention relates to a method for producing a bipolar transistor comprising a polysilicon emitter, according to which a collector region (12) of a first conductivity type and an adjacent base region (14) of a second conductivity type are created. At least one layer (16) consisting of an insulating material is then applied, said layer or layers being structured in such a way that at least one section of the base region (14) is exposed. A layer consisting of a polycrystalline semiconductor material of the first conductivity type, which is highly doped with doping atoms, is subsequently created, in such a way that the exposed section is essentially covered. A second layer (20) consisting of a highly conductive material is then created on the layer (18) consisting of the polycrystalline semiconductor material, forming a dual-layer emitter with the latter. At least one portion of the doping atoms of the first conductivity type of the highly doped polycrystalline semiconductor layer is then caused to diffuse into the base region (14), to create an emitter region (22) of the first conductivity type.

    Abstract translation: 用于制造双极多晶硅发射本发明的方法，首先产生一第一导电类型和相邻的第二导电型的基极区域（14）的集电极区域（12）。 现在，一个层（16）至少由绝缘材料，其特征在于，所述至少一个结构化的层，使得至少在基极区域（14）的一部分暴露施加。 接着，高度掺杂有第一导电类型掺杂原子的多晶半导体材料的层（18）中产生，使得基本上，所述暴露部分被覆盖。 现在，层（18）上的高导电材料的第二层（20）由多晶半导体材料制成，以形成具有一个发射极的双层相同的。 然后使至少所述第一导电类型，所述高度掺杂的多晶半导体层的掺杂剂原子的一部分，进入到基极区，以形成第一导电类型的发射极区（22）。

    MEMORY CELL, MEMORY CELL DEVICE AND METHOD FOR THE PRODUCTION THEREOF
    3.
    发明申请
    MEMORY CELL, MEMORY CELL DEVICE AND METHOD FOR THE PRODUCTION THEREOF 审中-公开
    存储器单元，存储器单元布置和制造方法

    公开(公告)号：WO0215276A3

    公开(公告)日：2002-06-06

    申请号：PCT/DE0102997

    申请日：2001-08-06

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： PALM HERBERT ,  WILLER JOSEF ,  GRATZ ACHIM ,  KRIZ JAKOB ,  ROEHRICH MAYK

    IPC: H01L21/8247 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/792

    Abstract: Each memory cell is a memory transistor which is provided with a gate electrode (2) on the upper surface of a semiconductor body. Said gate electrode is disposed in a trench between a source area (3) and a drain area (4) which are formed in the semiconductor material. The gate electrode is separated from the semiconductor material by dielectric material. A series of oxide nitride-oxide layers (5, 6, 7) is disposed between the source area and the drain area and between the drain area and the gate electrode in order to capture charge carriers on the source and drain.

    Abstract translation: 每个存储器单元是设置在半导体主体的顶表面上的存储器晶体管，其中栅极电极（2）设置在形成在半导体材料中的源极区（3）和漏极区（4）之间的沟槽中 形成。 栅电极通过介电材料与半导体材料分离。 至少在源区和栅电极之间以及在漏区和栅电极之间存在氧化物 - 氮化物 - 氧化物层序列（5,6,7），其适于在源极和漏极处捕获电荷载流子 被提供。

    Halbleiterstruktur und Verfahren zu deren Herstellung
    5.
    发明专利
    Halbleiterstruktur und Verfahren zu deren Herstellung 未知

    公开(公告)号：DE102012110060A1

    公开(公告)日：2013-05-23

    申请号：DE102012110060

    申请日：2012-10-22

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KRIZ JAKOB ,  URBANSKY NORBERT

    IPC: H01L21/768 ,  H01L23/522

    Abstract: Ausführungsformen betreffen ein Verfahren zum Herstellen einer Halbleiterstruktur (102), wobei das Verfahren Folgendes aufweist: Ausbilden einer Keimschicht (150) in direktem Kontakt mit einem dielektrischen Material; Ausbilden einer Maskierungsschicht (160) über der Keimschicht (150); Strukturieren der Maskierungsschicht (160), um die Keimschicht (150) freizulegen; Ausbilden einer Füllschicht (170) über der freigelegten Keimschicht (150) und Bewirken, dass die Keimschicht (150) mit der Dielektrikumsschicht (110) reagiert, so dass eine Barrierenschicht (130) zwischen der Füllschicht (170) und der Dielektrikumsschicht (110) ausgebildet wird.

    6.
    发明专利
    未知

    公开(公告)号：DE102004044686B4

    公开(公告)日：2006-08-31

    申请号：DE102004044686

    申请日：2004-09-15

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GOLLER KLAUS ,  KRIZ JAKOB

    IPC: H01L23/522 ,  H01L21/768

    Abstract: An integrated circuit arrangement containing a via is disclosed. The via has an upper section having greatly inclined sidewalls. A lower section of the via has approximately vertical sidewalls. In one embodiment, a liner layer is used as a hard mask in the production of the via and defines the position of the sections of the via.

    9.
    发明专利
    未知

    公开(公告)号：DE102004044686A1

    公开(公告)日：2006-03-16

    申请号：DE102004044686

    申请日：2004-09-15

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GOLLER KLAUS ,  KRIZ JAKOB

    IPC: H01L23/522 ,  H01L21/768

    Abstract: An integrated circuit arrangement containing a via is disclosed. The via has an upper section having greatly inclined sidewalls. A lower section of the via has approximately vertical sidewalls. In one embodiment, a liner layer is used as a hard mask in the production of the via and defines the position of the sections of the via.

    10.
    发明专利
    未知

    公开(公告)号：DE10260352A1

    公开(公告)日：2004-07-15

    申请号：DE10260352

    申请日：2002-12-20

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GOLLER KLAUS ,  FOESTE BERND ,  KRIZ JAKOB ,  BACHMANN JENS

    IPC: H01L27/08 ,  H01L21/822 ,  H01L21/768

    Abstract: To make the capacitor arrangement (110) a stack (124b) of the following layers is produced: a base electrode layer (14), a base dielectric layer (16), at least one central electrode layer (18), a dielectric layer covering (20) and an electrode layer covering (22). This layer (22) and the central electrode layer (18) are structured in the first lithographic process. The electrode layer covering (22a) and the base electrode layer (14) are structured using a second lithographic process. An independent claim is included for the corresponding integrated capacitor arrangement.

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