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公开(公告)号：WO0250838A2
公开(公告)日：2002-06-27
申请号：PCT/DE0104786
申请日：2001-12-18
Applicant: INFINEON TECHNOLOGIES AG , KAISER ROBERT , SCHAMBERGER FLORIAN
Inventor： KAISER ROBERT , SCHAMBERGER FLORIAN
Abstract: The invention relates to a circuit arrangement for controlling a programmable connection (1), which comprises a trigger circuit (2) for selecting and burning the fuse (1), and which comprises a shift register (3), with which an activating signal (B, B') can be supplied to the trigger circuit (2). In a preferred embodiment, a volatile memory location (5) can be provided in order to provide the data that initiates the burning. The circuit arrangement enables a burning of fuses (1) and thus permits the repair of defective memory locations in bulk storage devices even after a chip having the bulk storage device has been embedded. In addition, the aforementioned shift register (3) effectively prevents the occurrence of impermissibly high currents due to the simultaneous burning of too many fuses (1).
Abstract translation: 提供了一种用于驱动一可编程链路提供了一种电路装置（1），其包含（2）的驱动电路，用于选择和烧制熔丝（1）和一个移位寄存器（3）与该驱动电路（2）（活化乙 ，B“）可以被供给。 以提供可以提供一种非易失性存储单元（5）的优选实施例要烧制的数据。 本电路允许熔丝的燃烧（1），因此修复故障存储单元中的大容量存储甚至一个芯片，它具有大容量存储的铸造后。 另外，由过多的熔丝的同时烧成（1）有效地与所描述的移位寄存器（3）防止，可发生不可接受的高电流。
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公开(公告)号：DE10119125C1
公开(公告)日：2002-12-12
申请号：DE10119125
申请日：2001-04-19
Applicant: INFINEON TECHNOLOGIES AG
Inventor： KAISER ROBERT , SCHAMBERGER FLORIAN
IPC: G11C29/04 , G11C8/00 , G11C11/401 , G11C29/00
Abstract: A comparison method compares the address of a memory cell with a known address of a faulty memory cell in a semiconductor memory module. The module is subdivided into banks and has an address structure in which each address is associated with a bank that is organized in rows and columns and is defined by a row address, a column address and a bank address. Not only the row address is determined, but also the column address and the bank address when a memory access occurs. A bank is activated with a bank selection signal, and the access to a valid address of a faulty memory cell is indicated by an enable register.
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公开(公告)号：DE10118421C1
公开(公告)日：2002-11-07
申请号：DE10118421
申请日：2001-04-12
Applicant: INFINEON TECHNOLOGIES AG
Inventor： LE THOAI-THAI , SCHAFFROTH THILO , KAISER ROBERT , KUHNE SEBASTIAN
Abstract: The condition detector has two edge-triggered D-type flip-flops (10,11) controlled by different clock signals (CLKS,CLKA) for sampling a control signal (CKE) indicating the condition, coupled on the output side via respective pulse elements (12,13) to a resettable flip-flop (15), providing a feedback signal for one of the memory elements.
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公开(公告)号：DE10119144C1
公开(公告)日：2002-10-10
申请号：DE10119144
申请日：2001-04-19
Applicant: INFINEON TECHNOLOGIES AG
Inventor： KAISER ROBERT , SCHAMBERGER FLORIAN
Abstract: The data is stored in a memory bank having an addressable matrix structure. The elements selected from a group consisting of rows and columns, are subdivided into regions. The defect locations in each region are counted and compared with a threshold value. The comparison results are transmitted as an additional information along with the addresses of defect locations in the memory bank, to an external test device.
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公开(公告)号：DE10031946C2
公开(公告)日：2002-08-14
申请号：DE10031946
申请日：2000-06-30
Applicant: INFINEON TECHNOLOGIES AG
Inventor： KAISER ROBERT , SCHAFFROTH THILO
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Patent Agency Ranking
公开(公告)号：DE10063688A1
公开(公告)日：2002-07-18
申请号：DE10063688
申请日：2000-12-20
Applicant: INFINEON TECHNOLOGIES AG
Inventor： SCHAMBERGER FLORIAN , KAISER ROBERT
Abstract: A circuit configuration for driving a programmable link has a volatile memory cell, which is coupled to the fuse for the permanent storage of data stored in the volatile memory, and also a shift register, which enables data to be read out from the volatile memory cell and data to be written to the memory cell. In this case, a plurality of shift registers may be interconnected to form a shift register chain for the purpose of driving a plurality of fuses. The shift register chain thus enables fast writing and reading to/from the volatile memory with a low outlay on circuitry.
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公开(公告)号：DE10062092A1
公开(公告)日：2002-07-11
申请号：DE10062092
申请日：2000-12-13
Applicant: INFINEON TECHNOLOGIES AG
Inventor： KAISER ROBERT , SCHAMBERGER FLORIAN
Abstract: During a read routine at a location in a main memory area (1) a value is read out from a memory area and compared in a comparator (4) with a scheduled value from a scheduled value memory (5). By relying on a result from the comparison and on a read-mode control signal, the location is stored in an error location register (10). To test a memory area, a number of read routines are performed on the main memory area without storing the location in the error location store. A further read routine is carried out and the location is stored in the error location store depending on a result from the comparison. An Independent claim is also included for a method for testing a memory cell for a main memory area.
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18.发明专利
公开(公告)号：DE10062093A1
公开(公告)日：2002-05-02
申请号：DE10062093
申请日：2000-12-13
Applicant: INFINEON TECHNOLOGIES AG
Inventor： KAISER ROBERT , SCHAMBERGER FLORIAN
Abstract: The circuit comprises a comparator (4) for a data value with associated rated data value to determine a faulty address. The data value has been read-out of an addressed memory range of the memory field (1) during testing.The circuit has also a faulty address memory (9). Between the comparator and faulty address memory is fitted a switch (7) to deposit the address as faulty one in the faulty address memory, dependent on a control signal (Hit). Independent claims are included for an integrated circuit and method of faulty address suppression.
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公开(公告)号：DE10306620B4
公开(公告)日：2007-04-19
申请号：DE10306620
申请日：2003-02-18
Applicant: INFINEON TECHNOLOGIES AG
Inventor： FRANKOWSKY GERD , KAISER ROBERT
IPC: G01R31/28 , G01R19/165 , H01L21/66 , H01L23/544 , H01L23/58
Abstract: A switching device (4) selects one of several internal voltages (V0-Vn) for testing according to a selection signal. A comparator device (5) compares a test voltage dependent on the selected internal voltage with an externally preset reference voltage (VREF) and issues an error signal as a result. An independent claim is also included for a method for testing an integrated circuit with a test circuit.
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公开(公告)号：DE102004043050B4
公开(公告)日：2006-08-17
申请号：DE102004043050
申请日：2004-09-06
Applicant: INFINEON TECHNOLOGIES AG
Inventor： SPIRKL WOLFGANG , KILIAN VOLKER , KAISER ROBERT , BROX MARTIN
IPC: G01R31/3183 , G01R31/319 , G11C29/48
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