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    11.
    发明专利
    未知

    公开(公告)号：DE19825612C2

    公开(公告)日：2002-10-31

    申请号：DE19825612

    申请日：1998-06-08

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KAKOSCHKE RONALD ,  STOKAN REGINA

    IPC: H01L21/285 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532 ,  H01L21/8238

    Abstract: A semiconductor component has local silicon wiring. A first silicon region and a second silicon region are doped with dopants of opposite conductivity. The second silicon region is arranged at least partially over the first silicon region and is separated from it by an insulation layer. The insulation layer is formed with an opening. A conductive layer is disposed at the opening. The conductive layer is composed of a metal, a metal nitride or a combination thereof and connects the first and the second silicon regions electrically to one another.

    12.
    发明专利
    未知

    公开(公告)号：DE10110150A1

    公开(公告)日：2002-09-19

    申请号：DE10110150

    申请日：2001-03-02

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： WILLER JOSEF ,  KAKOSCHKE RONALD

    IPC: H01L27/10 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/788 ,  H01L29/792 ,  H01L21/8239

    Abstract: A method for producing bit lines for a memory cell array comprises as a first step the step of providing a layer structure which comprises a substrate having transistor wells implanted in a surface thereof, a sequence of storage medium layers provided on the surface of said substrate, and a gate region layer provided on said sequence of storage medium layers. Bit line recesses, which extend down to the sequence of storage medium layers, are produced in said gate region layer. Subsequently, insulating spacer layers are produced on lateral surfaces of said bit line recesses, whereupon a source/drain implantation is executed in the area of said bit line recesses, after a complete or partial removal of the sequence of storage medium layers. Following this, the substrate is exposed completely in the area of the bit line recesses, if this has not yet been done prior to the implantation. Subsequently, metallizations for producing metallic bit lines are produced on the exposed substrate, said metallizations being insulated from the gate region layer by the insulating spacer layers.

    13.
    发明专利
    未知

    公开(公告)号：DE19614011C2

    公开(公告)日：2002-06-13

    申请号：DE19614011

    申请日：1996-04-09

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KAKOSCHKE RONALD

    IPC: H01L21/8247 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L27/115

    Abstract: An avalanche breakdown from the buried channel to the substrate in a semiconductor component, in particular an EEPROM, is avoided by a local thickened portion of the gate dielectric. The thickened portion establishes an insulation structure at the transition to the tunnel dielectric. This produces a potential barrier which enables the gate dielectric and the tunnel dielectric to have the same thickness. The space requirement of such a cell is reduced.

    Integrated memory devices
    14.
    发明专利
    Integrated memory devices 未知

    公开(公告)号：GB2417131B

    公开(公告)日：2006-10-11

    申请号：GB0513538

    申请日：2005-07-01

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KAKOSCHKE RONALD ,  NIRSCHL THOMAS ,  SCHRUFER KLAUS ,  SHUM DANNY PAK-CHUM

    IPC: H01L29/70 ,  G11C16/04 ,  H01L27/115 ,  H01L29/861

    Abstract: A method of fabricating a memory device in a semiconductor substrate, the device having a memory array having a plurality of memory cell transistors arranged in rows and columns. The method includes forming a plurality of tunneling field effect transistors, forming a first well of the second doping type, forming a second well of the first doping type surrounding the first well, forming a first word line connected to a first row of memory cell transistors, forming a first bit line to control a voltage of doped drain regions of tunneling field effect transistors of a first column of memory cell transistors, and forming a second bit line parallel to the first bit line.

    Semiconductor memory device
    15.
    发明专利
    Semiconductor memory device 未知

    公开(公告)号：GB2417131A

    公开(公告)日：2006-02-15

    申请号：GB0513538

    申请日：2005-07-01

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KAKOSCHKE RONALD ,  NIRSCHL THOMAS ,  SCHRUFER KLAUS ,  SHUM DANNY PAK-CHUM

    IPC: H01L29/70 ,  G11C16/04 ,  H01L27/115 ,  H01L29/861

    Abstract: The memory device comprises an array of tunnel field effect transistors (TFETs) where a memory state of the device is determined by the quantity of charge stored on a floating gate. The charge stored on the floating gate is injected from an inversion layer formed in the device channel during programming. The device is configured with TFETs arranged in columns with buried bit lines connecting first conductivity type source regions and raised bitlines connecting second conductivity type drain regions. Wordlines interconnect the control gate lines of TFETs arranged in rows.

    SPEICHERBAUELEMENT und VORRICHTUNGEN UNTER VERWENDUNG VON FINFETs
    19.
    发明专利
    SPEICHERBAUELEMENT und VORRICHTUNGEN UNTER VERWENDUNG VON FINFETs 未知

    公开(公告)号：DE102008000319B4

    公开(公告)日：2014-12-18

    申请号：DE102008000319

    申请日：2008-02-15

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KAKOSCHKE RONALD ,  SCHRÜFER KLAUS

    IPC: H01L27/105 ,  H01L27/115 ,  H01L27/22 ,  H01L27/24

    Abstract: Speicherbauelement, umfassend: ein FinFET-Auswahlbauelement mit einem Steg (40) und ein Speicherelement (20), wobei das FinFET-Auswahlbauelement ein Kontaktelement (50) aufweist, das räumlich zwischen einer oberen Oberfläche des Stegs (40) und dem Speicherelement (20) angeordnet und elektrisch leitfähig an den Steg (40) gekoppelt ist, wobei das Speicherelement ein NVM-Speicherelement ist, und wobei das Kontaktelement (50) teilweise den Steg umhüllt, und wobei das Speicherelement (20) ausgewählt ist aus einer Gruppe von Speicherelementen bestehend aus PCRAM-, MRAM-, CBRAM- und FeRAM-Speicherelement.

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