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    11.
    发明专利
    未知

    公开(公告)号：DE50310011D1

    公开(公告)日：2008-07-31

    申请号：DE50310011

    申请日：2003-09-13

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HOFMANN FRANZ ,  LEHMANN VOLKER ,  RISCH LOTHAR ,  ROESNER WOLFGANG ,  SPECHT MICHAEL

    IPC: H01L21/8242 ,  H01L21/02 ,  H01L21/334 ,  H01L21/84 ,  H01L27/108 ,  H01L27/12 ,  H01L29/94

    Abstract: Semiconductor substrate comprises a carrier substrate (1), a semiconductor component layer (3), an insulating layer (2) arranged between the carrier substrate and the semiconductor component layer, recesses (P) formed in a surface facing the insulating layer in the carrier substrate, a dielectric layer (D) formed on the surface of the recesses and carrier substrate, and an electrically conducting layer (E2) formed in the recesses to produce capacitor electrodes. A further electrically conducting layer is formed in the carrier substrate to form capacitor counter electrodes in the region of the recesses. An Independent claim is also included for a process for the production of a semiconductor substrate.

    14.
    发明专利
    未知

    公开(公告)号：DE59813243D1

    公开(公告)日：2006-01-05

    申请号：DE59813243

    申请日：1998-09-04

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： RISCH LOTHAR ,  ROESNER WOLFGANG ,  RAMCKE TIES ,  JACOBS HERMANN

    IPC: G11C17/10 ,  H01L21/822 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/112

    Abstract: Resistors are connected between word lines and bit lines running transversely with respect thereto. The resistors have a higher resistance than the word lines and the bit lines. The bit lines are each connected to a sense amplifier which regulates the potential on the respective bit line to a reference potential and at which an output signal can be picked off. If one of the word lines is selected and all the other word lines are put at reference potential, then the resistance of the resistor, which is assigned to an information item, can be read from the output signal.

    15.
    发明专利
    未知

    公开(公告)号：DE50007390D1

    公开(公告)日：2004-09-16

    申请号：DE50007390

    申请日：2000-05-26

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ROESNER WOLFGANG ,  SCHULZ THOMAS ,  RISCH LOTHAR

    IPC: H01L29/417 ,  H01L21/20 ,  H01L21/336 ,  H01L29/786

    Abstract: A double gate MOSFET transistor and a method for fabricating it are described. In this case, a semiconductor layer structure of a transistor channel to be formed is embedded in a spacer material and contact-connected by source and drain regions which are filled into depressions that are etched on opposite sides of the semiconductor layer structure. Afterwards, the spacer material is etched out selectively and replaced by the electrically conductive gate electrode material.

    16.
    发明专利
    未知

    公开(公告)号：DE59706533D1

    公开(公告)日：2002-04-11

    申请号：DE59706533

    申请日：1997-05-02

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： RISCH LOTHAR ,  ROESNER WOLFGANG

    IPC: G11C11/38 ,  G11C11/34 ,  G11C11/40 ,  G11C11/404 ,  H01L27/10 ,  H01L27/28 ,  H01L51/05

    Abstract: Each memory cell of an array has a single-electron transistor and a single-electron memory element. The single-electron transistor is driven by a charge stored in the memory element. When a read voltage is applied, a current flows through the single-electron transistor which is dependent on the stored charge, but the stored charge in not changed. When a write voltage is applied, the magnitude of which is greater than the read voltage, then the stored charge is changed. The memory cells of the array are each connected between first lines and transverse second lines of a memory cell configuration.

    18.
    发明专利
    未知

    公开(公告)号：AT214194T

    公开(公告)日：2002-03-15

    申请号：AT97107314

    申请日：1997-05-02

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： RISCH LOTHAR ,  ROESNER WOLFGANG

    IPC: G11C11/38 ,  G11C11/34 ,  G11C11/40 ,  G11C11/404 ,  H01L27/10 ,  H01L27/28 ,  H01L51/05

    Abstract: Each memory cell of an array has a single-electron transistor and a single-electron memory element. The single-electron transistor is driven by a charge stored in the memory element. When a read voltage is applied, a current flows through the single-electron transistor which is dependent on the stored charge, but the stored charge in not changed. When a write voltage is applied, the magnitude of which is greater than the read voltage, then the stored charge is changed. The memory cells of the array are each connected between first lines and transverse second lines of a memory cell configuration.

    19.
    发明专利
    未知

    公开(公告)号：DE19950362C1

    公开(公告)日：2001-06-07

    申请号：DE19950362

    申请日：1999-10-19

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ROESNER WOLFGANG ,  SCHULZ THOMAS ,  RISCH LOTHAR ,  HOFMANN FRANZ

    IPC: H01L21/8242 ,  H01L27/108 ,  H01L27/12 ,  G11C11/401

    Abstract: The DRAM arrangement has several memory cells, each with storage (S) and transfer (T) transistors. A transfer transistor gate electrode is connected to a word line (W). The storage transistor has a floating gate electrode separated from a channel region by a first dielectric and connected to a source/drain region of the transfer transistor. The storage transistor has a control gate electrode separated from the floating gate electrode by a second dielectric and connected to the word line. A first source/drain region of the storage transistor is connected to a bit line (B) running transversely wrt. the word line.

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