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    SEMICONDUCTOR STRUCTURE PROVIDED WITH A COMPONENT CAPACITIVELY UNCOUPLED FROM THE SUBSTRATE
    1.
    发明申请
    SEMICONDUCTOR STRUCTURE PROVIDED WITH A COMPONENT CAPACITIVELY UNCOUPLED FROM THE SUBSTRATE 审中-公开
    WITH A衬底能力去耦分量的半导体结构

    公开(公告)号：WO03036723A2

    公开(公告)日：2003-05-01

    申请号：PCT/EP0209705

    申请日：2002-08-30

    Applicant: INFINEON TECHNOLOGIES AG ,  BOECK JOSEF ,  MEISTER THOMAS ,  SCHAEFER HERBERT ,  STENGL REINHARD

    Inventor： BOECK JOSEF ,  MEISTER THOMAS ,  SCHAEFER HERBERT ,  STENGL REINHARD

    IPC: H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L27/06

    CPC classification number: H01L21/84 ,  H01L21/76264 ,  H01L21/76283 ,  H01L27/1203

    Abstract: The invention concerns a semiconductor structure comprising a substrate (10), an insulating layer (14) arranged on one surface of the substrate (10), a layer (18) for components arranged on one surface (16) of the insulating layer (14) opposite the substrate (10), a semiconductor component (30a, 30b) arranged in the layer (18) for components and zone designed for capacitively uncoupling said semiconductor component (30a, 30b) relative to the substrate (10), said zone being formed by a space charge zone (96) formed in a region of the substrate (10) adjacent to the insulating layer (14).

    Abstract translation: 一种半导体结构，包括衬底（10），其被布置在所述基板（10），该表面面向远离所述基板的一个（10）的器件层（18）的一个表面（12）上的绝缘层（14）（16） 在绝缘层（14）设置，半导体装置（30A，30B），其是所述器件层（18）设置，以及用于半导体装置的电容性耦合的区域（30A，30B）在基板（10）的， 通过在形成于基板（10）空间电荷区中的绝缘层（14）区域中的相邻的一个（96）形成。

    BIPOLAR TRANSISTOR
    2.
    发明申请
    BIPOLAR TRANSISTOR 审中-公开
    双极型晶体管

    公开(公告)号：WO0159845A2

    公开(公告)日：2001-08-16

    申请号：PCT/EP0101324

    申请日：2001-02-07

    Applicant: INFINEON TECHNOLOGIES AG ,  FRANOSCH MARTIN ,  SCHAEFER HERBERT ,  MEISTER THOMAS ,  STENGL REINHARD

    Inventor： FRANOSCH MARTIN ,  SCHAEFER HERBERT ,  MEISTER THOMAS ,  STENGL REINHARD

    IPC: H01L21/331 ,  H01L29/732

    CPC classification number: H01L29/66287 ,  H01L29/7322

    Abstract: The invention relates to a bipolar transistor (20) and to a method for producing the same. In order to obtain an as low a transition resistance as possible between the feed line (51) and the base (42), an intermediate layer (70) is provided between the first (30) and the second (40) layer, said intermediate layer (70) being selectively etchable to the second layer (40). At least in the zone of the undercut (43) between the feed line (51) and the base (42) a base connection zone (45) is provided that can be adjusted independent of other production conditions. The inventive transistor is further characterized in that the intermediate layer (70) is removed in the contact zone (46) with the base (42).

    Abstract translation: 公开了一种双极型晶体管（20），以及用于其生产的方法。 所述双极晶体管（20）具有在其中设置的收集器（31）的第一，在基板（10）位于层（30），位于一个所述第一层（30）上的第二层（40）（碱切口 41）具有基部（42），至少一个另外的第三层（50）（第二层40上）设置并且其具有用于所述基部（42），其中，所述进料管线的进料管线（51）（51 ）（在过渡区域52），以直接接触的所述基部（42），并且其中所述第三层（50）具有一个具有发射极的发射极的切口（53），和至少一个底切（43），其在所述第二层 （40）下面的所述第一（30）和第三之间的基底切口（41）（50）层设置，其特征在于，所述基部（42）至少部分地在所述底切（43）。 为了获得所述供应管线（51）和底座（42）之间的最低可能的过渡电阻，根据它提供的是，第一（30）之间的本发明和第二（40）层，中间层（70）设置，所述中间层（70）选择性地 形成以蚀刻第二层（40），至少在该底切之间（43）供应线（51）和基座（42）的基极端子区域（45）被提供，其可被调节的独立于其他制造条件的区域中，并且该中间层 （70）位于所述接触区（46）与所述基部（42）。

    4.
    发明专利
    未知

    公开(公告)号：DE19947117B4

    公开(公告)日：2007-03-08

    申请号：DE19947117

    申请日：1999-09-30

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： STENGL REINHARD ,  REISINGER HANS ,  HANEDER THOMAS ,  BACHHOFER HARALD

    IPC: H01L21/8247 ,  H01L29/78 ,  G11C11/22 ,  H01L21/8246 ,  H01L27/105 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792

    Abstract: A first source-drain region, a channel region, and a second source-drain region are arranged one after another in a semiconductor substrate. At least the surface of the channel region and parts of the first source-drain region are covered by a dielectric layer. A ferroelectric layer is disposed on the surface of the dielectric layer between two polarization electrodes. A gate electrode is arranged on the surface of the dielectric layer. The thickness of the dielectric layer is dimensioned such that a remanent polarization of the ferroelectric layer, which is aligned between the two polarization electrodes, produces compensation charges in part of the channel region. The ferroelectric transistor is suitable as a memory cell for a memory cell configuration.

    7.
    发明专利
    未知

    公开(公告)号：DE10104776A1

    公开(公告)日：2002-08-22

    申请号：DE10104776

    申请日：2001-02-02

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： STENGL REINHARD ,  MEISTER THOMAS F ,  SCHAEFER HERBERT ,  FRANOSCH MARTIN

    IPC: H01L21/331 ,  H01L29/737 ,  H01L29/73 ,  H01L29/732

    Abstract: The invention relates to a method for producing a bipolar transistor having low base terminal resistance, a low defect density, and improved scalability, scalability referring to both the lateral scaling of the emitter window and the vertical scaling of the base width (low temperature budget). The temperature budget can be maintained at a low level in the base area, as no implantations are required in order to reduce the base terminal resistance. Furthermore, the difficulties related to point defects are largely avoided.

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