12.
    发明专利
    未知

    公开(公告)号:DE10297097T5

    公开(公告)日:2004-12-09

    申请号:DE10297097

    申请日:2002-07-31

    Abstract: Circuitry using fuse and anti-fuse latches (62) for selecting the number of input/output channels (98, 109) after encapsulation is disclosed. The various embodiments allow conventional bond pads (14, 16, 18) to be used for initial selection of the number of input/output channels prior to encapsulation. However, by providing different selection signals (52, 54), the number of input/output channels may be changed by the user at any time after encapsulation. Other embodiments employ "enable" latch circuits (133,135) allow the initial selection by the users at any time after encapsulation, and then at least one more subsequent selection.

    18.
    发明专利
    未知

    公开(公告)号:DE10202881B4

    公开(公告)日:2007-09-20

    申请号:DE10202881

    申请日:2002-01-25

    Abstract: The present invention provides a method of producing semiconductor chips (1a, 1b, 1c; 1a', 1b', 1c') with a protective chip-edge layer (21'', 22''), in particular for wafer level packaging chips, with the steps of: preparing a semiconductor wafer (1); providing trenches (21, 22) in the semiconductor wafer to establish chip edges on a first side of the semiconductor wafer (1); filling the trenches (21, 22) with a protective agent (21'; 22'); grinding back the semiconductor wafer (1) from a second side of the semiconductor wafer (1), which is opposite from the first side, to expose the trenches (21, 22) filled with the protective agent (21'; 22'); and cutting through the trenches (21, 22) filled with the protective agent (21'; 22'), so that the protective chip-edge layer (21'', 22'') comprising the protective agent (21', 22') remains on the chip edges.

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