公开(公告)号：DE10137341A1

公开(公告)日：2003-02-27

申请号：DE10137341

申请日：2001-07-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BONART DIETRICH ,  VOIGT PETER

IPC: H01L21/225 ,  H01L21/8242 ,  H01L27/108

Abstract: Process for forming a diffusion region, especially a diffusion contact, in a semiconductor substrate (20) comprises: (a) providing a first conducting region (30, 32) and a second conducting region (40) separately from each other through an intermediate region (25) of the substrate; (b) forming the diffusion region (50) in the intermediate region between the conducting regions by thermal diffusion of a doping agent (P) in the intermediate region; and (c) thermally initiating a conversion process in a partial region of the intermediate region. Preferably the conversion process is a chemical conversion, crystallization or oxidation process. A bulk silicon substrate, p-doped silicon or similar is used as semiconductor substrate, intermediate layer and/or partial region of the substrate. The doping agent is made from phosphorous.

公开(公告)号：DE102004043902B4

公开(公告)日：2007-04-05

申请号：DE102004043902

申请日：2004-09-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： VOIGT PETER ,  STRASSER MARC ,  FISCHER BJOERN ,  GRUENING ULRIKE VON SCHWERIN ,  SCHLOESSER TILL ,  WEIS ROLF

IPC: H01L27/108 ,  G11C11/404

公开(公告)号：DE10144912B4

公开(公告)日：2005-12-22

申请号：DE10144912

申请日：2001-09-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： VOIGT PETER ,  SCHNEIDER HELMUT

IPC: H01L21/8242

公开(公告)号：DE10328634B3

公开(公告)日：2004-10-21

申请号：DE10328634

申请日：2003-06-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： VOIGT PETER ,  ENDERS GERHARD

IPC: H01L21/334 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

Abstract: Production of a buried strap contact comprises back etching the inner electrode layer (102) in a trench, removing the exposed insulating layer (105) from the trench wall to form buried strap contact surfaces, depositing a liner layer (106) to cover the inner electrode layer in the trench and the exposed trench wall, forming a spacer layer with the material of the inner electrode layer on the liner layer on the trench wall, removing the exposed liner layer from the inner electrode layer in the trench, and filling the trench with the material of the inner electrode layer.

公开(公告)号：DE10212932A1

公开(公告)日：2003-10-16

申请号：DE10212932

申请日：2002-03-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： VOIGT PETER ,  ENDERS GERHARD

IPC: H01L21/8242 ,  H01L27/02 ,  H01L27/108 ,  H01L29/94

Abstract: A trench cell for use in a DRAM array includes a vertical selection transistor of a first conductivity type at the-seen in the bit line direction-first side of the trench hole, a blocking doping region near the surface, of a second conductivity type, is provided adjacent to the trench hole, the blocking doping region lying opposite the vertical selection transistor. As a result, leakage currents can be avoided and, in addition, the trench cells can be disposed at a shorter distance from one another.

公开(公告)号：DE10233916C1

公开(公告)日：2003-08-21

申请号：DE10233916

申请日：2002-07-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BONART DIETRICH ,  ENDERS GERHARD ,  VOIGT PETER

IPC: H01L21/8242 ,  H01L29/94 ,  H01L27/108

Abstract: Production of a vertical transistor in the upper section of a trench comprises preparing a single crystalline substrate (2) with a trench (4), lining the lower section of the trench with a storage dielectric (8) and filling with a conducting material (10), forming an auxiliary insulation layer on the conducting material, depositing an epitaxial semiconductor layer (26) on the exposed side walls of the upper section of the trench, removing the auxiliary insulation layer, depositing a thin nitride layer (32) which is thin enough only to partially impair a current flow, filling the trench with a doped further conducting material (34) to form an electrical connection the conducting material and a lower partial section of the epitaxial semiconductor layer, forming a gate dielectric on the exposed regions of the epitaxial semiconductor layer, and forming a gate electrode on the gate dielectric and a doping region in the upper partial region of the epitaxial semiconductor layer. An Independent claim is also included for a semiconductor storage cell having a trench capacitor and a vertical transistor. Preferred Features: The thin nitride layer is 04-0.8 nm thick and separates the further conducting material from the epitaxial semiconductor layer.

公开(公告)号：DE10144912A1

公开(公告)日：2003-03-27

申请号：DE10144912

申请日：2001-09-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： VOIGT PETER ,  SCHNEIDER HELMUT

IPC: H01L21/8242

Abstract: The zone (8) is introduced into the body of the semiconductor (1) in two stages. Between them, the material is back-etched.

公开(公告)号：DE102004043902A1

公开(公告)日：2006-03-16

申请号：DE102004043902

申请日：2004-09-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： VOIGT PETER ,  STRASSER MARC ,  FISCHER BJOERN ,  GRUENING ULRIKE VON SCHWERIN ,  SCHLOESSER TILL ,  WEIS ROLF

IPC: H01L27/108 ,  G11C11/404

Abstract: The transistor has a gate dielectric layer (11) between a gate-electrode and a canal region (81). The gate dielectric layer has a gate dielectric layer-thickness and a terminal dielectric layer (21) which is attached between a drain region (51) or a source region (41) and the gate-electrode. The terminal dielectric layer has a terminal dielectric layer-thickness, which is greater than gate dielectric layer-thickness. An independent claim is also included for a dynamic random access memory (DRAM) cell for attaching a memory capacitor to a field-effect transistor.

公开(公告)号：DE102004027425A1

公开(公告)日：2005-09-29

申请号：DE102004027425

申请日：2004-06-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： VOIGT PETER ,  ENDERS GERHARD

IPC: H01L21/033 ,  H01L21/3213 ,  H01L21/8234 ,  H01L21/8238

Abstract: A process for producing a trench (40) in a layer (14) on the surface of a substrate (10), comprises covering a primary layer section with a mask (16) which has a step at the edge (18). A second material is precipitated on the primary mask structure and on a section not covered by the mask. The second material is then etched, and a second mask structure made of a third material, is applied to the second section next to a spacer. The spacer is then removed by selective etching and the trench is etched in the layer.

公开(公告)号：DE10249650A1

公开(公告)日：2004-05-13

申请号：DE10249650

申请日：2002-10-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POPP MARTIN ,  ENDERS GERHARD ,  VOIGT PETER

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/78

Abstract: The method involves applying gate stacks adjacent to each other to a gate dielectric with a semiconducting substrate of first conductor type with constant sum of common stack width and separation of, determining angle for inclined implantation of first conductor type doping with self-adjustment to gate stack edges, whereby a dose variation compensates for a FET starting voltage variation caused by width variation about desired width. The method involves applying gate stacks adjacent to each other to a gate dielectric (5) with a semiconducting substrate (1) of a first conductor type (p) with a constant sum of a common width (b) and separation (c) of the gate stacks, determining an angle (alpha) for inclined implantation (I) of doping of the first conductor type with self-adjustment to the edges of the gate stacks, whereby a dose variation compensates for a FET starting voltage variation caused by a width variation about a desired width.