公开(公告)号：WO2004025693A3

公开(公告)日：2004-04-29

申请号：PCT/EP0308946

申请日：2003-08-12

Applicant: INFINEON TECHNOLOGIES AG ,  ENDERS GERHARD ,  FAUL JUERGEN ,  FISCHER BJOERN ,  HEINECK LARS ,  HIERLEMANN MATTHIAS ,  POPP MARTIN ,  VOIGT PETER

Inventor： ENDERS GERHARD ,  FAUL JUERGEN ,  FISCHER BJOERN ,  HEINECK LARS ,  HIERLEMANN MATTHIAS ,  POPP MARTIN ,  VOIGT PETER

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/8242

CPC classification number: H01L27/10873 ,  H01L21/26586 ,  H01L27/10888 ,  H01L29/66492 ,  H01L29/6656 ,  H01L29/66659

Abstract: The invention relates to a method for the production of a semi-conductor structure comprising a plurality of gate stacks (GS1 - GS8) which are arranged on a semi-conductor substrate (1). Said method comprises the following steps: applying the gate-stack (GS1 - GS8) to a gate dielectric (5) via the semi-conductor substrate (1); implanting doping (100, 105, 110, 120, 130; 105''', 110''', 120''', 130''', 140''') which is self-adjusted in relation to the edges of the gate stack (GS1 - GS8); and forming an side wall oxide (40) on the free side walls of the gate stack (GS1 - GS8) while at the same time forming diffused doping areas (100', 110', 120', 130'; 110''', 120''', 130''', 140''') below the gate stack. The invention also relates to said type of semi-conductor structure.

Abstract translation: 本发明提供了一种用于生产具有多个栅极堆栈（GS1 - GS8）的半导体结构的半导体衬底（1）上通过以下步骤制备：将所述栅极堆叠 - 上的栅极电介质（GS1 GS8）（5 ）在半导体衬底上（1）; 注入掺杂剂（100，105，110，120，130; 105 '' '110' ''，120 '''，130' ''，140 ''“）自对准到栅叠层的边缘（GS1 - GS8 ）; 以及形成在所述栅极堆叠（GS1 - GS8）的暴露的侧壁上形成侧壁氧化物（40）与扩散掺杂区的同时形成（100 '110' ，120'，130 '; 110 '''，120' ''，130 “”栅极边缘下”，140' ‘’）。 本发明还提供这样的半导体结构。

公开(公告)号：DE10318604A1

公开(公告)日：2004-11-25

申请号：DE10318604

申请日：2003-04-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ENDERS GERHARD ,  FISCHER BJOERN ,  SCHNEIDER HELMUT ,  VOIGT PETER

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/78

Abstract: The device has a semiconducting substrate (402) with a source region, a drain region and a channel region, whereby the source and drain regions are connected to source (404) and drain (406) electrodes, the channel region has first and second constriction regions connected in parallel with respect to the source and drain electrodes and a gate electrode (408) arranged above the first and second constriction channel regions.

公开(公告)号：DE10351030A1

公开(公告)日：2005-06-09

申请号：DE10351030

申请日：2003-10-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOLDBACH MATTHIAS ,  FREY ULRICH ,  FISCHER BJOERN

IPC: H01L21/336 ,  H01L21/8242 ,  H01L29/423 ,  H01L29/78 ,  H01L27/108 ,  G11C11/40

Abstract: Transistor structures, with one source/drain region connected to a charge storage device to be insulated includes an asymmetric gate conductor structure. At a first side wall, which faces the one source/drain region, the asymmetric gate conductor structure has a side wall oxide with a greater thickness and a bird's beak structure with a greater length than at an opposite, second side wall. An effective channel length is increased for the same feature size of the gate conductor structure. Memory cells can be realized in a higher density.

公开(公告)号：DE102023122081B3

公开(公告)日：2025-02-20

申请号：DE102023122081

申请日：2023-08-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HELL MICHAEL ,  LEENDERTZ CASPAR ,  ELPELT RUDOLF ,  FISCHER BJOERN

IPC: H10D30/60 ,  H10D12/00 ,  H10D62/10 ,  H10D62/832

Abstract: Eine Halbleitervorrichtung (10) weist einen Transistor auf. Der Transistor weist eine Vielzahl von in einem Halbleitersubstrat (100) ausgebildeten Gate-Gräben (111) auf, wobei die Gate-Gräben (111) das Halbleitersubstrat (100) in Stege (114) strukturieren. Ferner weist der Transistor eine in zumindest einem der Gate-Gräben (111) angeordnete Gate-Elektrode (110) auf. Ein Source-Gebiet (124), ein Kanalgebiet (122), ein Teil eines Stromspreizungsgebiets (126) sind in den Stegen (114) angeordnet. Die Halbleitervorrichtung (10) weist ferner eine Superjunction-Struktur (117) auf, die in einem größeren Abstand zum Source-Gebiet (124) als dem Kanalgebiet (122) angeordnet ist. Die Superjunction-Struktur (117) weist ein erstes Kompensationsgebiet (118) des ersten Leitfähigkeitstyps und ein zweites Kompensationsgebiet (119) des zweiten Leitfähigkeitstyps auf. Eine Dotierungskonzentration des dotierten Bereichs (120) des zweiten Leitfähigkeitstyps des Kanalgebiets (122) nimmt in einer die erste horizontale Richtung kreuzenden zweiten horizontalen Richtung von einem Gebiet nahe der Gate-Elektrode (110) zu einem zentralen Bereich des Stegs (114) ab.

公开(公告)号：DE102004043902A1

公开(公告)日：2006-03-16

申请号：DE102004043902

申请日：2004-09-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： VOIGT PETER ,  STRASSER MARC ,  FISCHER BJOERN ,  GRUENING ULRIKE VON SCHWERIN ,  SCHLOESSER TILL ,  WEIS ROLF

IPC: H01L27/108 ,  G11C11/404

Abstract: The transistor has a gate dielectric layer (11) between a gate-electrode and a canal region (81). The gate dielectric layer has a gate dielectric layer-thickness and a terminal dielectric layer (21) which is attached between a drain region (51) or a source region (41) and the gate-electrode. The terminal dielectric layer has a terminal dielectric layer-thickness, which is greater than gate dielectric layer-thickness. An independent claim is also included for a dynamic random access memory (DRAM) cell for attaching a memory capacitor to a field-effect transistor.

公开(公告)号：DE102004043902B4

公开(公告)日：2007-04-05

申请号：DE102004043902

申请日：2004-09-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： VOIGT PETER ,  STRASSER MARC ,  FISCHER BJOERN ,  GRUENING ULRIKE VON SCHWERIN ,  SCHLOESSER TILL ,  WEIS ROLF

IPC: H01L27/108 ,  G11C11/404

公开(公告)号：DE102004036461A1

公开(公告)日：2006-02-16

申请号：DE102004036461

申请日：2004-07-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LUYKEN JOHANNES R ,  HOFMANN FRANZ ,  FISCHER BJOERN ,  SPITZER ANDREAS

IPC: G11C11/404 ,  H01L27/108

Abstract: Electronic data memory device for a high read current The invention provides a memory device arranged on a substrate ( 401 ) and having at least one memory cell ( 100 ) The memory cell comprises a storage capacitor ( 200 ) for storing an electrical charge and a selection transistor ( 300 ) for selecting the memory cell ( 100 ). The selection transistor comprises a first conduction electrode ( 301 ), a second conduction electrode ( 302 ) and a control electrode ( 303 ) , the control electrode ( 303 ) being provided by a gate unit ( 400 ) having a fin ( 405 ) projecting from the substrate ( 401 ), which fin is surrounded by a gate oxide layer ( 406 ) and a gate electrode layer ( 403 ) in such a way that first and second gate elements ( 408 a , 408 b) are provided at opposite lateral areas of the fin ( 405 ), a third gate element ( 408 c) being provided at an area of the fin ( 405 ) that is parallel to the surface of the substrate ( 401 ).

公开(公告)号：DE102004047665B3

公开(公告)日：2006-02-16

申请号：DE102004047665

申请日：2004-09-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STRASSER MARC ,  STOEMMER RALPH ,  FISCHER BJOERN

IPC: H01L27/108

Abstract: An electronic component storage cell (8) comprises a capacitor (20) with electrodes (24, 26), a semiconductor switch, a bit conductor, and a metallic connection region. The semiconductor switch has a canal region (32) whose electrical conductivity can be controlled. The canal region and the metallic connection region (28) form a Schottky contact. A tunnel barrier layer is located between the metallic connection region and the canal region.

公开(公告)号：DE10306315A1

公开(公告)日：2004-09-02

申请号：DE10306315

申请日：2003-02-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOLDBACH MATTHIAS ,  FISCHER BJOERN ,  JAKSCHIK STEFAN ,  SCHLOESSER TILL

IPC: H01L21/02 ,  H01L21/28 ,  H01L21/316 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L21/336

Abstract: A semiconductor device comprises a first doping region (S) of first conductivity (n), a second doping region (D) of first conductivity, a channel region (K) arranged between the two regions, and a gate structure arranged over the channel region. The gate structure has a first gate dielectric (D1) made from a first material having a first thickness (d) and a first dielectric constant (k1) and a second gate dielectric (D2) made from a second material having a first thickness (d') and a first dielectric constant (k2.) : An independent claim is also included for the production of the semiconductor device.

公开(公告)号：DE10240429A1

公开(公告)日：2004-03-18

申请号：DE10240429

申请日：2002-09-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POPP MARTIN ,  ENDERS GERHARD ,  HEINECK LARS ,  VOIGT PETER ,  HIERLEMANN MATTHIAS ,  FISCHER BJOERN ,  FAUL JUERGEN

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/8242

Abstract: Production of a semiconductor structure comprises applying gate stacks (GS1-GS8) onto a gate dielectric (5) over a semiconductor substrate (1), implanting a dopant (100) which is self-adjusting to the edges of the gate stack, and forming a side wall oxide (40) on exposed side walls of the gate stack with simultaneous formation of diffused doping regions (100', 110', 120', 130') under the gate edge. An Independent claim is also included for a semiconductor structure produced by the above process.