公开(公告)号：DE10138510B4

公开(公告)日：2006-08-10

申请号：DE10138510

申请日：2001-08-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TEMMLER DIETMAR ,  WICH-GLASEN ANDREAS

IPC: H01L21/762

Abstract: The invention relates to a trench isolation with a self-aligning surface sealing and a fabrication method for said surface sealing. In this case, the surface sealing may have an overlap region of the substrate surface or a receded region into which extends an electrically conductive layer formed on the substrate surface.

公开(公告)号：DE10131237B4

公开(公告)日：2006-05-04

申请号：DE10131237

申请日：2001-06-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TEMMLER DIETMAR ,  RICHTER FRANK ,  POPP MARTIN ,  WICH-GLASEN ANDREAS

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06

Abstract: A transistor is provided which advantageously utilizes a part of the area which, in conventional transistors, is provided for the isolation between the transistors. In this case, the channel width can be enlarged in a self-aligned manner without the risk of short circuits. The field-effect transistor according to the invention has the advantage that it is possible to ensure a significant increase in the effective channel width for the forward current ION compared with previously used, conventional transistor structures, without having to accept a reduction of the integration density that can be attained. Thus, by way of example, the forward current I ON can be increased by up to 50%, without having to alter the arrangement of the active regions or of the trench isolation.

公开(公告)号：DE10210434A1

公开(公告)日：2003-10-23

申请号：DE10210434

申请日：2002-03-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： EFFERENN DIRK ,  MOLL HANS-PETER ,  WICH-GLASEN ANDREAS

IPC: H01L21/762 ,  H01L21/8238 ,  H01L21/8242

Abstract: The method for producing a shallow trench isolation for n- and p-channel field-effect transistors in a semiconductor module provides the following steps. A thermal oxide layer is applied in isolation trenches. A nitride liner is subsequently applied. In a further step, a mask is applied in the region in which n-channel field-effect transistors are intended to be produced. The nitride liner is removed around the mask. Finally, the mask is also removed. As a result, the properties of the n-channel field-effect transistors are improved, without impairing the properties of the p-channel field-effect transistors.

公开(公告)号：DE10110974C2

公开(公告)日：2003-07-24

申请号：DE10110974

申请日：2001-03-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WICH-GLASEN ANDREAS ,  TEMMLER DIETMAR

IPC: H01L21/762 ,  H01L21/20 ,  H01L21/76

公开(公告)号：DE10141841C1

公开(公告)日：2003-03-06

申请号：DE10141841

申请日：2001-08-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： EFFERENN DIRK ,  MOLL HANS-PETER ,  WICH-GLASEN ANDREAS ,  GRUNING VON SCHWERIN ULRIKE ,  RADECKER JOERG

IPC: H01L21/027 ,  H01L21/033 ,  H01L21/321 ,  H01L21/308 ,  H01L21/311 ,  H01L21/768

Abstract: A description is given of a method for a selective masking of a structure with a small structure surface with respect to a structure with a larger structure surface. To that end, the structures are filled with a covering layer. The covering layer is formed with a larger thickness above the first structure, which has the larger structure surface, than above the second structure. Afterward, the covering layer is removed by a homogeneous removal method, so that first the structure surface of the second structure is uncovered. A simple self-aligning method for fabricating a mask for uncovering the second structure is thus provided.

公开(公告)号：DE50114133D1

公开(公告)日：2008-08-28

申请号：DE50114133

申请日：2001-10-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MOLL HANS-PETER ,  WICH-GLASEN ANDREAS ,  TRUEBY ALEXANDER

IPC: H01L21/762

Abstract: A method for the fabrication of an integrated semiconductor component, in which at least one isolation trench is formed, a first layer of a nonconductive material is applied by a nonconformal deposition method, and a second layer of a nonconductive material is applied by a conformal deposition method at least to the back surface of the semiconductor component.

公开(公告)号：DE10210434B4

公开(公告)日：2007-12-27

申请号：DE10210434

申请日：2002-03-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： EFFERENN DIRK ,  MOLL HANS-PETER ,  WICH-GLASEN ANDREAS

IPC: H01L21/762 ,  H01L21/8238 ,  H01L21/8242

Abstract: The method for producing a shallow trench isolation for n- and p-channel field-effect transistors in a semiconductor module provides the following steps. A thermal oxide layer is applied in isolation trenches. A nitride liner is subsequently applied. In a further step, a mask is applied in the region in which n-channel field-effect transistors are intended to be produced. The nitride liner is removed around the mask. Finally, the mask is also removed. As a result, the properties of the n-channel field-effect transistors are improved, without impairing the properties of the p-channel field-effect transistors.

公开(公告)号：DE10214126A1

公开(公告)日：2003-10-23

申请号：DE10214126

申请日：2002-03-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WICH-GLASEN ANDREAS ,  POPP MARTIN

IPC: H01L21/265 ,  H01L21/28 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8234

Abstract: Process for producing a plurality of gate stacks approximately the same height and equidistant on a semiconductor substrate. The process includes providing a gate dielectric on the semiconductor substrate and applying and patterning at least a first layer and a second layer, above the first layer, to the gate dielectric to produce the gate stacks. An oblique implantation of an oxidation-inhibiting implantation species is carried out into two opposite, uncovered side faces of the second of the gate stacks, with respectively adjacent gate stacks serving to shadow the uncovered side faces of the first layer of the gate stacks. Oxidation to simultaneously form a first oxide layer on uncovered side faces of the first layer of the gate stacks and a second oxide layer on uncovered side faces of the second layer of the gate stacks is carried out, the thickness of the first oxide layer being greater than the thickness of the second oxide layer.

公开(公告)号：DE10152549A1

公开(公告)日：2003-05-15

申请号：DE10152549

申请日：2001-10-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POPP MARTIN ,  WICH-GLASEN ANDREAS ,  TEMMLER DIETMAR

IPC: H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

Abstract: Production of electrical contact region in micro-electronic semiconductor structure comprises: producing trench in substrate; forming insulating layer partially covering the trench wall and filling the trench with electrically conductive filler; removing the first filler from the trench up to a required depth a; removing the insulating layer up to a depth b; and forming electrical contact region. Production of an electrical contact region in a micro-electronic semiconductor structure comprises: producing a trench (4) in a substrate (1); forming an insulating layer (9) partially covering the trench wall and filling the trench with an electrically conducting filler (10); removing the first filler from the trench up to a required depth a; removing the insulating layer up to a depth b which is deeper than depth a; and forming an electrical contact region (13, 14) on the edge regions of the trench, in which the insulating layer is removed, in the region between the depth b up to the maximum to a processed upper edge of the filling of the trench. Preferred Features: The processed upper edge of the filling of the trench is produced through the surface of the first filler. An intermediate layer having a thickness d is deposited on the horizontal surface of the first filler through which the processed upper edge of the filling of the trench is produced.

公开(公告)号：DE10131276B4

公开(公告)日：2007-08-02

申请号：DE10131276

申请日：2001-06-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TEMMLER DIETMAR ,  RICHTER FRANK ,  POPP MARTIN ,  WICH-GLASEN ANDREAS

IPC: H01L29/423 ,  H01L29/78 ,  H01L21/336 ,  H01L29/49 ,  H01L29/786

Abstract: The invention relates to a field effect transistor in which the planar channel region on the upper surface of the elevation is extended in width by means of additional vertical channel regions on the lateral surfaces of the elevation. Said additional vertical channel regions connect directly to the planar channel region (vertical extended channel regions). Said field effect transistor has the advantage that a significant increase in the effective channel width for the current flow I ON can be guaranteed relative to conventional transistor structures used up until the present, without having to accept a reduction in the achievable integration density. Said field effect transistor furthermore has a low reverse current I OFF . The above advantages are achieved without the thickness of the gate insulators up to the region of the charge transfer tunnels having to be reduced or a reduced stability.