公开(公告)号：DE10344862B4

公开(公告)日：2007-12-20

申请号：DE10344862

申请日：2003-09-26

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： DIVAKARUNI RAMACHANDRA ,  FEHLAUER GERD T ,  KUDELKA STEPHAN ,  MANDELMAN JACK A ,  SCHROEDER UWE ,  TEWS HELMUT

IPC: H01L27/108 ,  H01L21/334 ,  H01L21/8242 ,  H01L29/94

Abstract: A trench capacitor memory cell structure is provided with includes a vertical collar region that suppresses current leakage of an adjacent vertical parasitic transistor that exists between the vertical MOSFET and the underlying trench capacitor. The vertical collar isolation, which has a vertical length of about 0.50 mum or less, includes a first portion that is present partially outside the trench and a second portion that is present inside the trench. The first portion of the collar oxide is thicker than said second portion oxide thereby reducing parasitic current leakage.

公开(公告)号：DE102006002940A1

公开(公告)日：2006-10-19

申请号：DE102006002940

申请日：2006-01-21

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： KUDELKA STEPHAN ,  SETTLEMEYER KENNETH ,  TEWS HELMUT

IPC: H01L21/8242

公开(公告)号：DE10350354A1

公开(公告)日：2004-05-27

申请号：DE10350354

申请日：2003-10-29

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： GLUSCHENKOV OLEG ,  TEWS HELMUT

IPC: H01L21/316 ,  H01L21/314 ,  H01L21/321 ,  H01L29/78 ,  H01L21/336

Abstract: Forming a vertical MOS transistor or making another three-dimensional integrated circuit structure in a silicon wafer exposes planes having at least two different crystallographic orientations. Growing oxide on different crystal planes is inherently at different growth rates because the inter-atomic spacing is different in the different planes. Heating the silicon in a nitrogen-containing ambient to form a thin layer of nitride and then growing the oxide through the thin nitrided layer reduces the difference in oxide thickness to less than 1%.

公开(公告)号：WO03090257B1

公开(公告)日：2004-03-04

申请号：PCT/DE0301205

申请日：2003-04-10

Applicant: INFINEON TECHNOLOGIES AG ,  BARTH HANS-JOACHIM ,  TEWS HELMUT

Inventor： BARTH HANS-JOACHIM ,  TEWS HELMUT

IPC: C25D5/50 ,  C25D7/12 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/768

CPC classification number: H01L21/76886

Abstract: The invention relates to a method for producing thin metal-containing layers (5C) having low electrical resistance, according to which a metal-containing initial layer (5A) having a first grain size is configured on a carrier material (2) in a first step. A locally restricted heated area (W) is then created and moved within the metal-containing initial layer (5A) in such a way that the metal-containing initial layer (5A) is recrystallized so as to create the metal-containing layer (5C) having a second grain size which is enlarged to the first grain size, whereby a metal-containing layer having improved electrical properties is obtained.

Abstract translation: 本发明涉及一种用于制造含有金属的薄层（5C）具有低的电阻，其特征在于，最初具有在载体材料（2）的第一粒度前体层（5A）含金属的形成的方法。 随后，以这样的方式产生在含有金属的起始层（5A）局部限制热范围（W）和移动，使得用于制备含有金属的层（5C）的含金属的输出层（5A）的再结晶具有增加至所述第一粒度的第二粒度进行。 以这种方式，具有改善的电特性的含金属层。

公开(公告)号：WO0041459A3

公开(公告)日：2001-05-10

申请号：PCT/DE0000047

申请日：2000-01-05

Applicant: INFINEON TECHNOLOGIES AG ,  SCHREMS MARTIN ,  DRESCHER DIRK ,  WURZER HELMUT ,  TEWS HELMUT

Inventor： SCHREMS MARTIN ,  DRESCHER DIRK ,  WURZER HELMUT ,  TEWS HELMUT

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/316 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/51

CPC classification number: H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/31604 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518

Abstract: The invention relates to a semiconductor element with at least one layer of tungsten oxide (WOx), optionally in a structured tungsten oxide (WOx) layer. The inventive semiconductor element is characterized in that the relative permittivity ( epsilon r) of the tungsten oxide layer (WOx) is higher than 50.

Abstract translation: 根据本发明，具有至少一个氧化钨的层（的WOx），半导体装置任选地提供氧化钨（WO x）的图形层。 本发明的半导体装置的特征在于，所述氧化钨（WO x）的相对介电常数（ε-r）为低于50更大

公开(公告)号：WO2005038930A2

公开(公告)日：2005-04-28

申请号：PCT/EP2004052333

申请日：2004-09-28

Applicant: INFINEON TECHNOLOGIES AG ,  TEWS HELMUT ,  FEHLHABER RODGER

Inventor： TEWS HELMUT ,  FEHLHABER RODGER

IPC: H01L21/033 ,  H01L21/308 ,  H01L21/336 ,  H01L29/423 ,  H01L29/786 ,  B81C1/00

CPC classification number: H01L29/7851 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L29/42384 ,  H01L29/66772 ,  H01L29/66795

Abstract: Disclosed is a structuring method, among other things. According to said method, a filling material (22) having a T-shaped cross section is used as a structuring mask in order to create structures with sublithographic dimensions, particularly a double-fin field effect transistor.

Abstract translation: 其中特别说明了一种图案化方法，其中使用T形横截面的填充材料（22）作为构图掩模以产生具有亚光刻尺寸的结构，特别是双鳍场效应晶体管。

公开(公告)号：WO2005038922A2

公开(公告)日：2005-04-28

申请号：PCT/EP2004052216

申请日：2004-09-16

Applicant: INFINEON TECHNOLOGIES AG ,  TEWS HELMUT

Inventor： TEWS HELMUT

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10841 ,  H01L27/1082 ,  H01L27/10823 ,  H01L27/10832 ,  H01L27/10858 ,  H01L27/10864 ,  H01L27/10876 ,  H01L29/161 ,  H01L29/4916 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/7827 ,  Y10T29/41

Abstract: Disclosed is a field effect transistor (37), among other things, which comprises a monocrystalline control area (34). The inventive field effect transistor (37) provides a certain degree of freedom concerning the circuitry design and can be produced in a simple manner.

Abstract translation: 进行了说明，除其他外，一个场效应晶体管（37）具有单晶控制部（34）。 所述场效应晶体管（37），用于电路设计提供了自由和能够容易地制造。

公开(公告)号：WO2006076991A3

公开(公告)日：2006-10-26

申请号：PCT/EP2005056641

申请日：2005-12-09

Applicant: INFINEON TECHNOLOGIES AG ,  KAKOSCHKE RONALD ,  TEWS HELMUT

Inventor： KAKOSCHKE RONALD ,  TEWS HELMUT

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L21/823418 ,  H01L21/2815 ,  H01L27/088 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/7311 ,  H01L29/78 ,  H01L29/7835

Abstract: The invention inter alia relates to a method for producing a tunnel field-effect transistor (T1). The inventive method is characterized by producing differently doped connecting areas (28, 80) by means of self-aligned implantation methods.

Abstract translation: 其中，说明用于制造隧道场效应晶体管（T1）的方法。 通过自对准注入技术产生不同掺杂类型的端子区（28,80）。

公开(公告)号：WO2004057660A2

公开(公告)日：2004-07-08

申请号：PCT/DE0304046

申请日：2003-12-09

Applicant: INFINEON TECHNOLOGIES AG ,  TEWS HELMUT ,  FEHLHABER RODGER

Inventor： TEWS HELMUT ,  FEHLHABER RODGER

IPC: H01L21/28 ,  H01L21/8234 ,  H01L21/84 ,  H01L21/336

CPC classification number: H01L21/2815 ,  H01L21/28114 ,  H01L21/823425 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/84

Abstract: The invention relates to a method for producing: a sublithographic gate structure; an associated field effect transistor; an associated inverter, and; an associated inverter structure. A sublithographic gate structure (SG) having slight variations in the critical dimensions thereof can be directly produced on the lateral walls of a lithographically structured mask (M0, 2) by the conformal formation of a gate insulation layer (3) and of a gate layer with subsequently executed anisotropic etching.

Abstract translation: 本发明涉及一种用于制造亚光刻栅极结构，相关联的场效应晶体管和相关联的逆变器以及相关联的逆变器结构的，具有光刻图案化掩模的侧壁（M0，2）保形形成栅极绝缘层（3）和栅极层 已执行以下各向异性蚀刻（SG）可以在直接的临界尺寸亚光刻栅极结构的小变化来制造。

公开(公告)号：WO03090257A2

公开(公告)日：2003-10-30

申请号：PCT/DE0301205

申请日：2003-04-10

Applicant: INFINEON TECHNOLOGIES AG ,  BARTH HANS-JOACHIM ,  TEWS HELMUT

Inventor： BARTH HANS-JOACHIM ,  TEWS HELMUT

IPC: C25D5/50 ,  C25D7/12 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/00

CPC classification number: H01L21/76886

Abstract: The invention relates to a method for producing thin metal-containing layers (5C) having low electrical resistance, according to which a metal-containing initial layer (5A) having a first grain size is configured on a carrier material (2) in a first step. A locally restricted heated area (W) is then created and moved within the metal-containing initial layer (5A) in such a way that the metal-containing initial layer (5A) is recrystallized so as to create the metal-containing layer (5C) having a second grain size which is enlarged to the first grain size, whereby a metal-containing layer having improved electrical properties is obtained.

Abstract translation: 本发明涉及一种用于制造含有金属的薄层（5C）具有低的电阻，其特征在于，最初具有在载体材料（2）的第一粒度前体层（5A）含金属的形成的方法。 随后，以这样的方式产生在含有金属的起始层（5A）局部限制热范围（W）和移动，使得用于制备含有金属的层（5C）的含金属的输出层（5A）的再结晶具有增加至所述第一粒度的第二粒度进行。 以这种方式，得到具有改善的电性能的含金属层。