公开(公告)号：JP2005094005A

公开(公告)日：2005-04-07

申请号：JP2004266297

申请日：2004-09-14

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHENG KANGGUO ,  CHIDAMBARRAO DURESETI ,  DIVAKARUNI RAMA ,  GLUSCHENKOV OLEG G

IPC: H01L21/8242 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L27/108 ,  H01L29/78

CPC classification number: H01L27/10864 ,  H01L27/10867 ,  H01L27/10876 ,  H01L27/10888

Abstract: PROBLEM TO BE SOLVED: To provide a method and structure of a vertical strained silicon device.
SOLUTION: A trench capacitor vertical-transistor DRAM cell in an SiGe wafer compensates for overhang of a pad nitride, by forming an epitaxial strained silicon layer on trench walls that improves transistor mobility, removes voids from the polysilicon filling, and reduces resistance on the bit line contact. Another feature is that by forming a vertical strained silicon channel, the performance of the vertical device is improved.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供垂直应变硅器件的方法和结构。 解决方案：SiGe晶片中的沟槽电容器垂直晶体管DRAM单元通过在沟槽壁上形成外延应变硅层来补偿衬垫氮化物的突出，从而提高晶体管的迁移率，去除多晶硅填充物的空隙，并降低电阻 在位线上联系。 另一个特征是通过形成垂直应变硅通道，提高了垂直装置的性能。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004363595A

公开(公告)日：2004-12-24

申请号：JP2004159279

申请日：2004-05-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BELYANSKY MICHAEL P ,  DIVAKARUNI RAMA ,  ECONOMIKOS LAERTIS ,  JAMMY RAJARAO ,  SETTLEMYER JR KENNETH T ,  SHAFER PADRAIC C

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L21/76229

Abstract: PROBLEM TO BE SOLVED: To provide a method for filling up a separation trench in a silicon integrated circuit having at least one p-n junction or a phase boundary of different materials before forming a separation structure.
SOLUTION: This method relates to filling of the separation trench and a capacitor trench including a perpendicular field-effect transistor (FET) having aspect ratios up to a maximum of 60 (or p-n junction at an arbitrary front level or the phase boundary of the different materials) obtained through a process. The process comprises a step of coating a spin-on material based on silazane with low molecular weight, a step of performing prebake of the coated material at temperature less than about 450°C within oxygen atmosphere, a step of converting the stress of the material by heating within H
2 O atmosphere at intermediate temperature in the range from 450°C-800°C, a step of obtaining a material stable up to a maximum of 1000°C, which has compressive stress which can be adjusted by changing process parameters resulting from heating again within O
2 atmosphere at high temperature, and which has durability sufficiently resisting to CMP having an etching rate comparable to that of oxide dielectrics formed using the high-density plasma (HDP) technique.
COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JP2001223271A

公开(公告)日：2001-08-17

申请号：JP2001002760

申请日：2001-01-10

Applicant: IBM

Inventor： DIVAKARUNI RAMA ,  NESBIT LARRY A ,  RADENS CARL J

IPC: H01L23/522 ,  H01L21/28 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To simultaneously form a line interconnection of a bit line or the like and borderless contact to a diffused part such as bit line contact. SOLUTION: A semiconductor substrate contains a previously patterned gate stack 12 on the substrate, is covered with a first dielectric substance 40 for forming a first level 42 and then deposited with a second dielectric substance 44 to form a second level 46. A line interconnection opening 62 is formed at a second level 46 by a lithography and etching. The etching is continued to a microcrystallized region of an array region 30 of the substrate, and formed with a borderless contact opening between the gate stacks 12 corresponding to the line interconnection such as an opening of the bit line or the like. These openings are filled with one or more conductors to form the contact with the diffused part such as bit line contact or the like corresponding to the line interconnection of the bit line or the like.

公开(公告)号：JP2004193614A

公开(公告)日：2004-07-08

申请号：JP2003409522

申请日：2003-12-08

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHUDZIK MICHAEL PATRICK ,  DENNARD ROBERT H ,  DIVAKARUNI RAMA ,  FURMAN BRUCE KENNETH ,  JAMMY RAJARAO ,  NARAYAN CHANDRASEKHAR ,  PURUSHOTHAMAN SAMPATH ,  SHEPARD JR JOSEPH F ,  TOPOL ANNA WANDA

IPC: H01L23/12 ,  H01L23/50 ,  H01L25/04 ,  H01L25/18 ,  H01L29/40 ,  H05K1/16 ,  H05K3/46

CPC classification number: H05K1/162 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2924/01019 ,  H01L2924/01055 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/30105 ,  H05K1/167 ,  H05K3/4602 ,  H05K2201/09809

Abstract: PROBLEM TO BE SOLVED: To provide a structure for an integrated carrier equipped with high frequency and high speed passive components for computing. SOLUTION: A carrier 200 for a semiconductor component 102 is provided, which has passive components 3010 integrated in its substrate. The passive components 3010 include decoupling components, such as capacitors and resistors. A set of connections 210 is integrated in a close electrical proximity to the supported components. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2002026146A

公开(公告)日：2002-01-25

申请号：JP2001180648

申请日：2001-06-14

Applicant: IBM

Inventor： DIVAKARUNI RAMA ,  JAMMY RAJARAO ,  BYOON WAI KIMU ,  MANDELMAN JACK A ,  SUDO AKIRA ,  TOBBEN DIRK

IPC: H01L21/8242 ,  H01L27/108 ,  H01L29/94

Abstract: PROBLEM TO BE SOLVED: To provide a structure and a method for a trench-type capacitor improved in its charge holding capability. SOLUTION: The memory device includes a trench 23 which is formed on a substrate and has an upper part. A collar oxide film 21 is arranged at the upper part of the trench. A collar oxide film includes a pedestal 25. A conductor is charged in the trench. The pedestal reduces a leak of charges in the conductor. The method for forming the memory device, having the collar oxide film having the pedestal collar, is also disclosed.

公开(公告)号：DE60138000D1

公开(公告)日：2009-04-30

申请号：DE60138000

申请日：2001-10-15

Applicant: IBM

Inventor： ADKISSON JAMES W ,  AGNELLO PAUL D ,  BALLANTINE ARNE W ,  DIVAKARUNI RAMA ,  JONES ERIN C ,  NOWAK EDWARD J ,  RANKIN JED H

IPC: H01L21/336 ,  H01L29/161 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786

Abstract: A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.

公开(公告)号：AT519228T

公开(公告)日：2011-08-15

申请号：AT00103964

申请日：2000-02-25

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： DIVAKARUNI RAMA ,  GRUENING ULRIKE ,  KIM BYEONG Y ,  MANDELMAN JACK ,  NESBIT LARRY ,  RADENS CARL

IPC: H01L27/108 ,  H01L21/8242

Abstract: A semiconductor device including a substrate. At least one pair of deep trenches is arranged in the substrate. A collar lines at least a portion of a wall of each deep trench. A deep trench fill fills each deep trench. A buried strap extends completely across each deep trench over each deep trench fill and each collar. An isolation region is arranged between the deep trenches. A dielectric region overlies each buried strap in each deep trench.

公开(公告)号：AT426246T

公开(公告)日：2009-04-15

申请号：AT01308767

申请日：2001-10-15

Applicant: IBM

Inventor： ADKISSON JAMES W ,  AGNELLO PAUL D ,  BALLANTINE ARNE W ,  DIVAKARUNI RAMA ,  JONES ERIN C ,  NOWAK EDWARD J ,  RANKIN JED H

IPC: H01L21/336 ,  H01L29/161 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786

Abstract: A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.