公开(公告)号：US09899270B2

公开(公告)日：2018-02-20

申请号：US14233320

申请日：2012-12-07

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Qiuxia Xu ,  Huilong Zhu ,  Gaobo Xu ,  Huajie Zhou ,  Qingqing Liang ,  Dapeng Chen ,  Chao Zhao

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/823828 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7833

Abstract: There is disclosed a method for manufacturing a semiconductor device comprising two opposite types of MOSFETs formed on one semiconductor substrate, the method comprising: forming a portion of the MOSFET on the semiconductor substrate, said portion of said MOSFET comprising source/drains regions located in the semiconductor substrate, a dummy gate stack located between the source/drain region and above the semiconductor substrate and a gate spacer surrounding the dummy gate stack; removing the dummy gate stack of said MOSFET to form a gate opening which exposes the surface of the semiconductor substrate; forming an interfacial oxide layer on the exposed surface of the semiconductor structure; forming a high-K gate dielectric on the interfacial oxide layer within the gate opening; forming a first metal gate layer on the high-K gate dielectric; implanting doping ions in the first metal gate layer; forming a second metal gate layer on the first metal gate layer to fill up the gate opening; and annealing to diffuse and accumulate the doping ions at an upper interface between the high-K gate dielectric and the first metal gate layer and at a lower interface between the high-K gate dielectric and the interfacial oxide, and generating an electric dipole at the lower interface between the high-K gate dielectric and the interfacial oxide by interfacial reaction.

公开(公告)号：US09773707B2

公开(公告)日：2017-09-26

申请号：US14838628

申请日：2015-08-28

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Guilei Wang ,  Jinbiao Liu ,  Jianfeng Gao ,  Junfeng Li ,  Chao Zhao

IPC: H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L21/3215

CPC classification number: H01L21/823828 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/3215 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/66545 ,  H01L29/7845

Abstract: There is provided a method for manufacturing a semiconductor device, including: providing a semiconductor substrate having a plurality of openings formed thereon by removing a sacrificial gate; filling the openings with a top metal layer having compressive stress; and performing amorphous doping with respect to the top metal layer in a PMOS device region. Thus, it is possible to effectively improve carrier mobility of an NMOS device, and also to reduce the compressive stress in the PMOS device region to ensure a desired performance of the PMOS device.

公开(公告)号：US20160268124A1

公开(公告)日：2016-09-15

申请号：US14821203

申请日：2015-08-07

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Xinyu Liu ,  Sen Huang ,  Xinhua Wang ,  Ke Wei ,  Wenwu Wang ,  Junfeng Li ,  Chao Zhao

IPC: H01L21/02 ,  H01L23/00

CPC classification number: H01L21/02271 ,  C23C16/0245 ,  C23C16/303 ,  H01L21/02164 ,  H01L21/02315 ,  H01L21/0254 ,  H01L21/02664

Abstract: A method for manufacturing a low interface state device includes performing a remote plasma surface process on a III-Nitride layer on a substrate; transferring the processed substrate to a deposition cavity via an oxygen-free transferring system; and depositing on the processed substrate in the deposition cavity. The deposition may be low pressure chemical vapor deposition (LPCVD). The interface state between a surface dielectric and III-Nitride material may be significantly decreased by integrating a low impairment remote plasma surface process and LPCVD.

Abstract translation: 低接口状态器件的制造方法包括在基板上的III-氮化物层上进行远程等离子体表面处理; 通过无氧转移系统将经处理的基底转移至沉积腔; 并沉积在沉积腔中的处理过的衬底上。 沉积可以是低压化学气相沉积（LPCVD）。 通过集成低损伤远程等离子体表面工艺和LPCVD，可以显着降低表面电介质和III-氮化物材料之间的界面状态。

公开(公告)号：US09412657B2

公开(公告)日：2016-08-09

申请号：US14943706

申请日：2015-11-17

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huicai Zhong ,  Chao Zhao ,  Huilong Zhu

IPC: H01L21/4763 ,  H01L21/768

CPC classification number: H01L21/486 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/49827

Abstract: In a method for manufacturing a semiconductor, a Through Silicon Via (TSV) template wafer and production wafers form a sandwich structure, in which the TSV template wafer has TSV structures uniformly distributed therein, for providing electrical connection between the production wafers to form 3D interconnection. The TSV template wafer is obtained by thinning a semiconductor wafer, which facilitates reducing the difficulty in etching and filling. Connection parts are provided on the TSV template wafer, for convenience of interconnection between the overlying and underlying production wafers, which facilitates reducing the difficulty in alignment and improving the convenience of design of electrical connection for 3D devices.

Abstract translation: 在制造半导体的方法中，透明硅（TSV）模板晶片和生产晶片形成夹层结构，其中TSV模板晶片具有均匀分布在其中的TSV结构，用于在生产晶片之间提供电连接以形成3D互连 。 通过减薄半导体晶片获得TSV模板晶片，这有助于降低蚀刻和填充的难度。 在TSV模板晶片上提供连接部件，以方便上层和下面的生产晶圆之间的互连，这有助于降低对准难度，并提高3D设备电气连接设计的便利性。

公开(公告)号：US09406549B2

公开(公告)日：2016-08-02

申请号：US14647393

申请日：2012-12-20

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu ,  Jun Luo ,  Chunlong Li ,  Jian Deng ,  Chao Zhao

IPC: H01L21/321 ,  H01L21/265 ,  H01L21/3105 ,  H01L21/762 ,  H01L29/10 ,  H01L29/66 ,  H01L21/308 ,  H01L21/311 ,  H01L21/8234 ,  H01L21/3213

CPC classification number: H01L21/76229 ,  H01L21/26513 ,  H01L21/308 ,  H01L21/31053 ,  H01L21/31056 ,  H01L21/31105 ,  H01L21/32115 ,  H01L21/32132 ,  H01L21/823481 ,  H01L29/1083 ,  H01L29/66795 ,  H01L29/6681

Abstract: A planarization process, the process including performing first sputtering on a material layer, with an area of the material layer which has a relatively low loading condition for sputtering shielded by a first shielding layer, removing the first shielding layer, and performing second sputtering on the material layer to planarize the material layer.

Abstract translation: 平面化处理，该方法包括在材料层上进行第一溅射，其中材料层的面积具有相对低的负载条件，用于由第一屏蔽层屏蔽的溅射，去除第一屏蔽层，以及在第二溅射 材料层以平坦化材料层。

公开(公告)号：US20150262883A1

公开(公告)日：2015-09-17

申请号：US14722597

申请日：2015-05-27

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu ,  Jun Luo ,  Chunlong Li ,  Jian Deng ,  Chao Zhao

IPC: H01L21/8234 ,  H01L21/265 ,  H01L21/321 ,  H01L29/66 ,  H01L21/306 ,  H01L21/308 ,  H01L21/3105 ,  H01L29/10

CPC classification number: H01L21/823431 ,  H01L21/265 ,  H01L21/30604 ,  H01L21/3083 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31056 ,  H01L21/31105 ,  H01L21/32115 ,  H01L21/32132 ,  H01L21/76229 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/1083 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/6681 ,  H01L29/7848

Abstract: A planarization process is disclosed. The method includes forming a trench in an area of a material layer which has a relatively high loading condition for sputtering. The method further includes sputtering the material layer to make the material layer flat.

Abstract translation: 公开了平面化处理。 该方法包括在具有相对高的溅射负载条件的材料层的区域中形成沟槽。 该方法还包括溅射材料层以使材料层平坦。

公开(公告)号：US09111863B2

公开(公告)日：2015-08-18

申请号：US14119869

申请日：2012-12-12

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Chunlong Li ,  Junfeng Li ,  Jiang Yan ,  Chao Zhao

IPC: H01L21/338 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L21/28123 ,  H01L21/32139 ,  H01L29/513 ,  H01L29/66545

Abstract: A method for manufacturing a dummy gate in a gate-last process and a dummy gate in a gate-last process are provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer amorphous silicon; depositing top-layer amorphous silicon on the ONO structured hard mask; depositing a hard mask layer on the top-layer amorphous silicon, and trimming the hard mask layer so that the trimmed hard mask layer has a width less than or equal to 22 nm; and etching the top-layer amorphous silicon, the ONO structured hard mask and the bottom-layer amorphous silicon in accordance with the trimmed hard mask layer, and removing the hard mask layer and the top-layer amorphous silicon.

Abstract translation: 提供了一种在门最后处理中制造伪栅极的方法和在栅极最后工艺中的伪栅极。 该方法包括：提供半导体衬底; 在半导体衬底上生长栅极氧化层; 在栅极氧化物层上沉积底层非晶硅; 在底层非晶硅上沉积ONO结构的硬掩模; 在ONO结构化的硬掩模上沉积顶层非晶硅; 在顶层非晶硅上沉积硬掩模层，并修剪硬掩模层，使得修整的硬掩模层具有小于或等于22nm的宽度; 并根据修整的硬掩模层蚀刻顶层非晶硅，ONO结构的硬掩模和底层非晶硅，以及去除硬掩模层和顶层非晶硅。

公开(公告)号：US11127783B2

公开(公告)日：2021-09-21

申请号：US16177999

申请日：2018-11-01

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu ,  Junjie Li ,  Chao Zhao

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/12 ,  H01L43/10

Abstract: A Magnetic Random Access Memory (MRAM), a method of manufacturing the same, and an electronic device including the same are provided. The MRAM includes a substrate, an array of memory cells arranged in rows and columns, bit lines, and word lines. The memory cells each include a vertical switch device and a magnetic tunnel junction on the switch device and electrically connected to a first terminal of the switch device. An active region of the switch device at least partially includes a single-crystalline semiconductor material. Each of the memory cell columns is disposed on a corresponding bit line, and a second terminal of each of the respective switch devices in the memory cell column is electrically connected to the corresponding bit line. Each of the word lines is electrically connected to a control terminal of the respective switch devices of the respective memory cells in a corresponding memory cell row.

公开(公告)号：US10141408B2

公开(公告)日：2018-11-27

申请号：US14651980

申请日：2014-03-18

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Kunpeng Jia ,  Yajuan Su ,  Huilong Zhu ,  Chao Zhao

IPC: H01L21/04 ,  H01L29/16 ,  H01L29/24 ,  H01L29/167 ,  H01L21/265 ,  H01L21/266 ,  H01L21/283 ,  H01L29/45 ,  H01L21/426 ,  H01L21/441 ,  H01L21/477 ,  H01L21/324 ,  H01L21/285

Abstract: A method and an arrangement for reducing a contact resistance of a two-dimensional crystal material are provided. An example method may include forming a contact material layer on a two-dimensional crystal material layer; performing ion implantation; and performing thermal annealing.

公开(公告)号：US10062775B2

公开(公告)日：2018-08-28

申请号：US15368098

申请日：2016-12-02

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Sen Huang ,  Xinyu Liu ,  Xinhua Wang ,  Ke Wei ,  Qilong Bao ,  Wenwu Wang ,  Chao Zhao

IPC: H01L21/00 ,  H01L29/00 ,  H01L29/778 ,  H01L29/66 ,  H01L29/205 ,  H01L29/20 ,  H01L29/15 ,  H01L21/306

CPC classification number: H01L29/7786 ,  H01L21/30621 ,  H01L29/1066 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/432 ,  H01L29/66462

Abstract: A GaN-based power electronic device and a method for manufacturing the same is provided. The GaN-based power electronic device comprising a substrate and an epitaxial layer over the substrate. The epitaxial layer comprises a GaN-based heterostructure layer, a superlattice structure layer and a P-type cap layer. The superlattice structure layer is provided over the heterostructure layer, and the P-type cap layer is provided over the superlattice structure layer. By using this electronic device, gate voltage swing and safe gate voltage range of the GaN-based power electronic device manufactured on the basis of the P-type cap layer technique may be further extended, and dynamic characteristics of the device may be improved. Therefore, application process for the GaN-based power electronic device that is based on the P-type cap layer technique will be promoted.