公开(公告)号：DE102018131365A1

公开(公告)日：2019-07-11

申请号：DE102018131365

申请日：2018-12-07

Applicant: INTEL CORP

Inventor： KANG UKSONG ,  CRISS KJERSTEN ,  AGARWAL RAJAT ,  HALBERT JOHN

IPC: G06F12/00

Abstract: Ein von einem Speicher durchgeführtes Verfahren wird beschrieben. Das Verfahren beinhaltet das Erkennen erster Bits aus einer ersten aktivierten Spalte, die mit einer ersten Sub-Wortleitungsstruktur verknüpft ist, zeitgleich mit dem Erkennen zweiter Bits aus einer zweiten aktivierten Spalte, die mit einer zweiten Sub-Wortleitungsstruktur verknüpft ist. Das Verfahren beinhaltet außerdem das Bereitstellen der ersten Bits an ein und derselben ersten Bitposition in verschiedenen Lesewörtern einer Burst-Lesesequenz und das Bereitstellen der zweiten Bits an ein und derselben zweiten Bitposition in den verschiedenen Lesewörtern der Burst-Lesesequenz.

公开(公告)号：HK1063230A1

公开(公告)日：2004-12-17

申请号：HK04105981

申请日：2004-08-10

Applicant: INTEL CORP

Inventor： HALBERT JOHN ,  WILLIAMS MICHAEL ,  BONELLA RANDY ,  DODD JAMES

IPC: G11C20090101 ,  G06F20090101 ,  G06F13/42

Abstract: The present invention provides a system and method for providing reliable transmission in a buffered memory system. The system includes memory devices, a memory controller, data buffers, an address/command buffer, and a clock circuit. The memory controller sends data, address information, status information and command information, to the memory devices and receives data from the memory devices. The buffers interconnect the memory devices and the memory controller. The clock circuit is embedded in the addr/cmd buffer. The clock circuit takes an input clock and outputs an output clock to the data buffers and/or the memory devices to control clock-skew to the data buffers and/or the memory devices.

公开(公告)号：DE10196641T1

公开(公告)日：2003-08-28

申请号：DE10196641

申请日：2001-09-14

Applicant: INTEL CORP

Inventor： HALBERT JOHN ,  WILLIAMS MICHAEL ,  BONELLA RANDY ,  DODD JAMES

IPC: G06F13/42 ,  G06F13/00

Abstract: The present invention provides a system and method for providing reliable transmission in a buffered memory system. The system includes memory devices, a memory controller, data buffers, an address/command buffer, and a clock circuit. The memory controller sends data, address information, status information and command information, to the memory devices and receives data from the memory devices. The buffers interconnect the memory devices and the memory controller. The clock circuit is embedded in the addr/cmd buffer. The clock circuit takes an input clock and outputs an output clock to the data buffers and/or the memory devices to control clock-skew to the data buffers and/or the memory devices.

公开(公告)号：EP3198440A4

公开(公告)日：2018-04-04

申请号：EP15844023

申请日：2015-09-08

Applicant: INTEL CORP

Inventor： BONEN NADAV ,  BAINS KULJIT ,  HALBERT JOHN

IPC: G06F11/10 ,  G06F12/00 ,  G06F13/16

CPC classification number: G06F11/1076 ,  G06F11/1004 ,  G06F11/1048

Abstract: Providing access to an external memory controller to internal error correction bits from a memory device for use as metadata bits by the memory controller. In a first mode the memory device applies internal error correction bits for internal error correction at the memory device. In a second mode the memory device provides access to the internal error correction bits to the memory controller to allow the memory controller to use the data.

公开(公告)号：DE10196635B4

公开(公告)日：2011-06-16

申请号：DE10196635

申请日：2001-09-14

Applicant: INTEL CORP

Inventor： HALBERT JOHN ,  BONELLA RANDY

IPC: G11C29/12 ,  G11C29/14 ,  G11C29/48

公开(公告)号：AT428163T

公开(公告)日：2009-04-15

申请号：AT04810426

申请日：2004-11-05

Applicant: INTEL CORP

Inventor： HALBERT JOHN ,  FREEMAN CHRIS ,  WILLIAMS MICHAEL ,  BAINS KILJIT ,  ELLIS ROBERT ,  VOGT PETE

IPC: G09F13/16 ,  G06F13/16

Abstract: Method and apparatus for use with buffered memory modules are included among the embodiments. In exemplary systems, the memory module has a buffer that receives memory commands and data, and then presents those commands and data to physical memory devices through a separate interface. The buffer has the capability to accept an implicit memory command, i.e., a command that does not contain a fully-formed memory device command, but instead instructs the memory module buffer to form one or more fully-formed memory device commands to perform memory operations. Substantial memory channel bandwidth can be saved, for instance, with a command that instructs a memory module to clear a region of memory or copy a region to a second area in memory. Other embodiments are described and claimed.

公开(公告)号：AU8906701A

公开(公告)日：2002-04-02

申请号：AU8906701

申请日：2001-09-14

Applicant: INTEL CORP

Inventor： HALBERT JOHN ,  BONELLA RANDY M

IPC: G11C5/00 ,  G06F13/16

Abstract: The present invention utilizes a buffer to isolate a stack of memory devices, thereby taking advantage of the increased memory density available from stacked memory devices while reducing capacitive loading. A memory module in accordance with the present invention may include a stack of memory devices and a buffer coupled to the first and second memory devices and arranged to capacitively isolate the first and second memory devices from a bus. In a memory system in accordance with the present invention, multiple buffered stacks of memory devices are preferably coupled in a point-to-point arrangement, thereby further reducing capacitive loading.

公开(公告)号：AU9113801A

公开(公告)日：2002-03-26

申请号：AU9113801

申请日：2001-09-18

Applicant: INTEL CORP

Inventor： HALBERT JOHN ,  BONELLA RANDY ,  LAM CHUNG ,  DODD JAMES

IPC: G06F13/16 ,  G06F12/00 ,  G06F13/40 ,  G06F13/42 ,  G11C5/02 ,  G11C5/14 ,  G11C8/12

Abstract: A plurality of memory modules interface through a daisy-chain providing a point-to-point connection for each memory module. The first and the last memory module in the daisy chain each connect to a separate memory controller port forming a ring circuit. A distinct set of signals connect the memory modules in each direction. A junction circuit in each memory module provides line isolation, a coupling to the adjoining memory modules in the daisy chain, or in the case of the first and last memory module in the daisy chain, a memory module and a memory controller, and a data synchronization circuit. Each junction circuit provides as well as voltage conversion so that the memory devices on a memory module operate at a different voltage than the memory controller, and multiplexing/de-multiplexing so that a lesser number of lines interface with each junction circuit.

公开(公告)号：DE112011105909T5

公开(公告)日：2014-09-11

申请号：DE112011105909

申请日：2011-12-02

Applicant: INTEL CORP

Inventor： SHOEMAKER KENNETH ,  VOGT PETE ,  SCHAEFER ANDRE ,  MORROW WARREN ,  KIM JIN ,  HALBERT JOHN

IPC: H01L27/10 ,  H01L21/8242 ,  H01L27/108

Abstract: Dynamische Operationen für Operationen für einen Stapelspeicher mit Schnittstelle, die Offset-Kopplungsstrukturen bereitstellt. Eine Ausführungsform des Speichergeräts schließt ein Systemelement und einen Speicherstapel ein, der mit dem Systemelement gekoppelt ist, wobei der Speicherstapel eine oder mehrere Speicherchiplagenschichten einschließt. Jede Speicherchiplagenschicht schließt eine erste Fläche und eine zweite Fläche ein, wobei die zweite Fläche jeder Speicherchiplagenschicht eine Schnittstelle einschließt, um Datenschnittstellenpins der Speicherchiplagenschicht mit Datenschnittstellenpins einer ersten Fläche eines gekoppelten Elementes zu koppeln. Die Schnittstelle jeder Speicherchiplagenschicht schließt Verbindungen ein, die einen Offset zwischen jedem der Datenschnittstellenpins der Speicherchiplagenschicht und einem entsprechenden Datenschnittstellenpin der Datenschnittstellenpins des gekoppelten Elementes bereitstellen.

公开(公告)号：AT481713T

公开(公告)日：2010-10-15

申请号：AT04815687

申请日：2004-12-23

Applicant: INTEL CORP

Inventor： HALBERT JOHN ,  ELLIS ROBERT ,  BAINS KULJIT ,  FREEMAN CHRIS

IPC: G11C7/10 ,  G11C11/4096

Abstract: Provision and use of sets of isolators to enable the caching of the contents of at least one row of memory cells within a subarray of a bank of a memory device by a row of sense amplifiers associated with the subarray to enable faster access to read the contents of that at least one row through a read operation causing the data to read from the row of sense amplifiers versus from the row of memory cells, directly.