公开(公告)号：DE112006002559T5

公开(公告)日：2008-08-28

申请号：DE112006002559

申请日：2006-10-26

Applicant: INTEL CORP

Inventor： MOHANAVELU RAVINDRAN ,  MARTIN AARON ,  KESLING DAWSON ,  SALMON JOE ,  RASHID MAMUN UR

IPC: G06F1/10

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for a clocking architecture using a bidirectional clock. In an embodiment, a chip includes a bidirectional clock port capable of being statically configured to receive or to transmit a reference clock. In one embodiment, the chip includes a first port to receive data and a second port, wherein the chip repeats at least a portion of the data that it receives on the first port to a transmitter at the second port. Other embodiments are described and claimed.

公开(公告)号：DE112006001738T5

公开(公告)日：2008-05-29

申请号：DE112006001738

申请日：2006-06-29

Applicant: INTEL CORP

Inventor： MARTIN AARON ,  TO HING ,  RASHID MAMUN ,  SALMON JOE

IPC: G06F13/16 ,  G06F1/10

Abstract: De-skew is performed on a nibble-by-nibble basis where a nibble is not limited to four bits.

公开(公告)号：DE112006001042T5

公开(公告)日：2008-04-03

申请号：DE112006001042

申请日：2006-04-25

Applicant: INTEL CORP

Inventor： MARTIN AARON ,  HANUOLU PARVAN ,  MOONEY RANDY

IPC: H03H11/04 ,  H04B3/14 ,  H04L27/01

Abstract: A continuous-time equalizer includes a first transconductance circuit to set a gain of an amplified signal in a link and a second transconductance circuit to set a zero frequency in a transfer function of the equalizer. The zero frequency controls a frequency range of the signal amplified in the link based on the gain set by the first transconductance circuit.

公开(公告)号：GB2445698B

公开(公告)日：2010-11-03

申请号：GB0807407

申请日：2006-10-26

Applicant: INTEL CORP

Inventor： MOHANAVELU RAVINDRAN ,  MARTIN AARON ,  KESLING DAWSON ,  SALMON JOE ,  RASHID MAMUN UR

IPC: G06F1/04 ,  G06F1/10

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for a clocking architecture using a bidirectional clock. In an embodiment, a chip includes a bidirectional clock port capable of being statically configured to receive or to transmit a reference clock. In one embodiment, the chip includes a first port to receive data and a second port, wherein the chip repeats at least a portion of the data that it receives on the first port to a transmitter at the second port. Other embodiments are described and claimed.

公开(公告)号：GB2445698A

公开(公告)日：2008-07-16

申请号：GB0807407

申请日：2006-10-26

Applicant: INTEL CORP

Inventor： MOHANAVELU RAVINDRAN ,  MARTIN AARON ,  KESLING DAWSON ,  SALMON JOE ,  RASHID MAMUN UR

IPC: G06F1/04 ,  H03K19/0175

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for a clocking architecture using a bidirectional clock. In an embodiment, a chip includes a bidirectional clock port capable of being statically configured to receive or to transmit a reference clock. In one embodiment, the chip includes a first port to receive data and a second port, wherein the chip repeats at least a portion of the data that it receives on the first port to a transmitter at the second port. Other embodiments are described and claimed.

公开(公告)号：GB2441241A

公开(公告)日：2008-02-27

申请号：GB0719677

申请日：2006-04-25

Applicant: INTEL CORP

Inventor： MARTIN AARON ,  HANUOLU PARVAN ,  MOONEY RANDY

IPC: H03H11/04 ,  H04B3/14 ,  H04L25/03

Abstract: A continuous-time equalizer includes a first transconductance circuit to set a gain of an amplified signal in a link and a second transconductance circuit to set a zero frequency in a transfer function of the equalizer. The zero frequency controls a frequency range of the signal amplified in the link based on the gain set by the first transconductance circuit.

公开(公告)号：GB2440878A

公开(公告)日：2008-02-13

申请号：GB0722950

申请日：2006-06-29

Applicant: INTEL CORP

Inventor： MARTIN AARON ,  TO HING ,  RASHID MAMUN ,  SALMON JOE

IPC: G06F13/16 ,  G06F1/10

Abstract: De-skew is performed on a nibble-by-nibble basis where a nibble is not limited to four bits.