-
公开(公告)号：EP0847551A4
公开(公告)日：2001-11-21
申请号：EP96926742
申请日：1996-07-17
Applicant: INTEL CORP
Inventor： PELEG ALEXANDER D , YAARI YAACOV , MITTAL MILLIND , MENNEMEIER LARRY M , EITAN BENNY , GLEW ANDREW F , DULONG CAROLE , KOWASHI EIICHI , WITT WOLF
IPC: G06F5/00 , G06F7/544 , G06F7/57 , G06F7/60 , G06F9/30 , G06F9/302 , G06F9/315 , G06F9/38 , G06F15/78 , G06F7/00 , G06F7/02 , G06F7/38 , G06F7/50 , G06F7/52
CPC classification number: G06F7/57 , G06F7/49921 , G06F7/49994 , G06F7/5443 , G06F7/607 , G06F9/30014 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/3013 , G06F17/10 , G06F17/147 , G06F2207/382 , G06F2207/3828
Abstract: An apparatus for including in a processor a set of instructions that support operations on packed data required by typical multimedia applications. In one embodiment, the invention includes a processor having a storage area (150), a decoder (165), and a plurality of circuits (130). The plurality of circuits provide for the execution of a number of instructions to manipulate packed data. In this embodiment, these instructions include pack, unpack, packed multiply, packed add, packed subtract, packed compare, and packed shift.
-
公开(公告)号：HK1099095A1
公开(公告)日：2007-08-03
申请号：HK07105278
申请日：2007-05-18
Applicant: INTEL CORP
Inventor： PELEG ALEXANDER D , YAARI YAACOV , MITTAL MILLIND , MENNEMEIER LARRY M , EITAN BENNY , GLEW ANDREW F , DULONG CAROLE , KOWASHI EIICHI , WITT WOLF
IPC: G06F20060101 , G06F5/00 , G06F7/544 , G06F7/57 , G06F7/60 , G06F9/30 , G06F9/302 , G06F9/315 , G06F9/38 , G06F15/78
Abstract: An apparatus comprising: a first storage area operable to have stored therein a first packed data containing at least an A 1 , an A 2 , an A 3 , and an A 4 element; a second storage area operable to have stored therein a second packed data containing at least a B 1 , a B 2 , a B 3 , and a B 4 element; a multiply circuit including a first multiplier coupled to said first storage area to receive said A 1 and coupled to said second storage area to receive said B 1 ; a second multiplier coupled to said first storage area to receive said A 2 and coupled to said second storage are to receive said B 2 ; a third multiplier coupled to said first storage area to receive said A 3 and coupled to said second storage area to receive said B 3 ; a fourth multiplier coupled to said first storage area to receive said A 4 and coupled to said second storage area to receive said B 4 ; a first adder coupled to said first multiplier and said second multiplier; a second adder coupled to said third multiplier and said fourth multiplier; and a third storage area coupled to said first adder and said second adder, said third storage area having at least a first field and a second field, said first field for saving an output of said first adder as a first data element of a third packed data, said second field for saving an output of said second adder as a second data element of said third packed data.
-
公开(公告)号：HK1016301A1
公开(公告)日：1999-10-29
申请号：HK99101368
申请日：1999-04-07
Applicant: INTEL CORP
Inventor： DULONG CAROLE , MENNEMEIER LARRY M , PELEG ALEXANDER D , BUI TUAN H , KOWASHI EIICHI , MITTAL MILLIND , EITAN BENNY , FISHER STEPHEN A , MAYTAL BENNY
Abstract: A computer system which includes a multimedia input device which generates an audio or video input signal and a processor coupled to the multimedia input device. The system further includes a storage device coupled to the processor and having stored therein a signal processing routine for multiplying and accumulating input values representative of the audio or video input signal. The signal processing routine, when executed by the processor, causes the processor to perform several steps. These steps include performing a packed multiply add on a first set of values packed into a first source and a second set of values packed into a second source each representing input signals to generate a packed intermediate result. The packed intermediate result is added to an accumulator to generate a packed accumulated result in the accumulator. These steps may be iterated with the first set of values and portions of the second set of values to the accumulator to generate the packed accumulated result. Subsequent thereto, the packed accumulated result in the accumulator is unpacked into a first result and a second result and the first result and the second result are added together to generate an accumulated result.
-
公开(公告)号：AU1500497A
公开(公告)日：1998-09-03
申请号：AU1500497
申请日：1997-02-27
Applicant: INTEL CORP
Inventor： FISCHER STEPHEN , MENNEMEIER LARRY M , PELEG ALEXANDER D , DULONG CAROLE , KOWASHI EIICHI
Abstract: A method and apparatus for performing complex digital filters. According to one aspect of the invention, a computer system generally having a transmitting unit, a processor, and a storage device is described. The storage device is coupled to the processor and has stored therein a routine. When executed by the processor, the routine causes the processor to perform a digital filter on unfiltered data items using complex coefficients to generate an output data stream. Execution of the routine causes the processor to perform outer and inner loops. The outer loop steps through corresponding relationships between the complex coefficients and the unfiltered data items. Each of these corresponding relationships is used by the digital filter to generate the output data stream. The inner loop steps the complex coefficients. Within the inner loop, the unfiltered data item corresponding to the current complex coefficient is determined according to the current corresponding relationship. Then, in response to receiving an instruction, eight data elements are read and used to generate a currently calculated complex number. As a result of the manner in which these eight data elements are stored, the currently calculated complex number represents the product of the current complex coefficient and its corresponding unfiltered data item. The currently calculated complex number is then added to the current output packed data. As a result, the current output packed data stores the sum of the complex numbers generated in the current inner loop.
-
公开(公告)号：AU1296497A
公开(公告)日：1997-07-14
申请号：AU1296497
申请日：1996-12-17
Applicant: INTEL CORP
Inventor： ORENSTEIN DORON , VAKKALAGADDA RAMAMOHAN R , GLEW ANDREW F , MENNEMEIER LARRY M , PELEG ALEXANDER D , BISTRY DAVID , MITTAL MILLIND , DULONG CAROLE , KOWASHI EIICHI , EITAN BENNY , WECHSLER OFRI , LIN DERRICK
Abstract: A method and apparatus for executing different sets of instructions that cause a processor to perform different data type operations on different physical registers files that logically appear to software as a single aliased register file. According to one aspect of the invention, a processor is provided that includes at least two physical register files-one for executing scalar data type operations and the other for executing packed data type operations. In addition, the processor includes a transition unit that is configured to cause the two physical register files to logically appear to software executing on the processor as a single logical register file.
-
Patent Agency Ranking
公开(公告)号：DE19681660C2
公开(公告)日：2000-11-02
申请号：DE19681660
申请日：1996-12-17
Applicant: INTEL CORP
Inventor： GLEW ANDREW , VAKKALAGADDA RAMAMOHAN R , LIN DERRICK , MENNEMEIER LARRY M , PELEG ALEXANDER D , BISTRY DAVID , MITTAL MILLIND , DULONG CAROLE , KOWASHI EIICHI , EITAN BENNY
Abstract: A method for executing different sets of instructions that cause a processor to perform different data type operations in a manner that is invisible to various operating system techniques, that promotes good programming practices, and that is invisible to existing software conventions. According to one aspect of the invention, a data processing apparatus executes a first set of instructions of a first instruction type on what at least logically appears to software as a single logical register file. While the data processing apparatus is executing the first set of instructions, the single logical register file appears to be operated as a flat register file. In addition, the data processing apparatus executes a first instruction of a second instruction type using the logical register file. However, while the data processing apparatus is executing the first instruction, the logical register file appears to be operated as a stack referenced register file. Furthermore, the data processing apparatus alters all tags in a set of tags corresponding to the single logical register file to a non-empty state sometime between starting the execution of the first set of instructions and completing the execution of the first instruction. The tags identifying whether registers in the single logical register file are empty or non-empty.
-
公开(公告)号：BR9610095A
公开(公告)日：1999-02-17
申请号：BR9610095
申请日：1996-07-17
Applicant: INTEL CORP
Inventor： WITT WOLF , MENNEMEIR LARRY M , KOWASHI EEICHI , PELEG ALEXANDER D , DULONG CAROLE , GLEW ANDREW F , MITTAL MILLIND , EITAN BENNY , YAARI YAACOV
IPC: G06F5/00 , G06F7/544 , G06F7/57 , G06F7/60 , G06F9/30 , G06F9/302 , G06F9/315 , G06F9/38 , G06F15/78 , G06F7/00 , G06F7/38 , G06F7/52 , G06F7/50
Abstract: An apparatus comprising: a first storage area operable to have stored therein a first packed data containing at least an A 1 , an A 2 , an A 3 , and an A 4 element; a second storage area operable to have stored therein a second packed data containing at least a B 1 , a B 2 , a B 3 , and a B 4 element; a multiply circuit including a first multiplier coupled to said first storage area to receive said A 1 and coupled to said second storage area to receive said B 1 ; a second multiplier coupled to said first storage area to receive said A 2 and coupled to said second storage are to receive said B 2 ; a third multiplier coupled to said first storage area to receive said A 3 and coupled to said second storage area to receive said B 3 ; a fourth multiplier coupled to said first storage area to receive said A 4 and coupled to said second storage area to receive said B 4 ; a first adder coupled to said first multiplier and said second multiplier; a second adder coupled to said third multiplier and said fourth multiplier; and a third storage area coupled to said first adder and said second adder, said third storage area having at least a first field and a second field, said first field for saving an output of said first adder as a first data element of a third packed data, said second field for saving an output of said second adder as a second data element of said third packed data.
-
公开(公告)号：DE19681660T1
公开(公告)日：1998-10-29
申请号：DE19681660
申请日：1996-12-17
Applicant: INTEL CORP
Inventor： GLEW ANDREW , VAKKALAGADDA RAMAMOHAN R , LIN DERRICK , MENNEMEIER LARRY M , PELEG ALEXANDER D , BISTRY DAVID , MITTAL MILLIND , DULONG CAROLE , KOWASHI EIICHI , EITAN BENNY
Abstract: A method for executing different sets of instructions that cause a processor to perform different data type operations in a manner that is invisible to various operating system techniques, that promotes good programming practices, and that is invisible to existing software conventions. According to one aspect of the invention, a data processing apparatus executes a first set of instructions of a first instruction type on what at least logically appears to software as a single logical register file. While the data processing apparatus is executing the first set of instructions, the single logical register file appears to be operated as a flat register file. In addition, the data processing apparatus executes a first instruction of a second instruction type using the logical register file. However, while the data processing apparatus is executing the first instruction, the logical register file appears to be operated as a stack referenced register file. Furthermore, the data processing apparatus alters all tags in a set of tags corresponding to the single logical register file to a non-empty state sometime between starting the execution of the first set of instructions and completing the execution of the first instruction. The tags identifying whether registers in the single logical register file are empty or non-empty.
-
公开(公告)号：PL325231A1
公开(公告)日：1998-07-06
申请号：PL32523196
申请日：1996-08-07
Applicant: INTEL CORP
Inventor： PELEG ALEXANDER D , MITTAL MILLIND , MENNEMEIER LARY M , EITAN BENNY , DULONG CAROLE , KOWASHI EIICHI , WITT WOLF , LIN DERRICK CHU , BINDAL AHMET
-
公开(公告)号：AU1468297A
公开(公告)日：1997-07-17
申请号：AU1468297
申请日：1996-12-24
Applicant: INTEL CORP
Inventor： DULONG CAROLE , MENNEMEIER LARRY M , PELEG ALEXANDER D , BUI TUAN H , KOWASHI EIICHI , MITTAL MILLIND , EITAN BENNY , FISHER STEPHEN A , MAYTAL BENNY
Abstract: A computer system which includes a multimedia input device which generates an audio or video input signal and a processor coupled to the multimedia input device. The system further includes a storage device coupled to the processor and having stored therein a signal processing routine for multiplying and accumulating input values representative of the audio or video input signal. The signal processing routine, when executed by the processor, causes the processor to perform several steps. These steps include performing a packed multiply add on a first set of values packed into a first source and a second set of values packed into a second source each representing input signals to generate a packed intermediate result. The packed intermediate result is added to an accumulator to generate a packed accumulated result in the accumulator. These steps may be iterated with the first set of values and portions of the second set of values to the accumulator to generate the packed accumulated result. Subsequent thereto, the packed accumulated result in the accumulator is unpacked into a first result and a second result and the first result and the second result are added together to generate an accumulated result.
-
-
-
-
-
-
-
-
-
Search Results
50
records
(took 0.022 seconds)
