公开(公告)号：US20190121041A1

公开(公告)日：2019-04-25

申请号：US16090024

申请日：2016-03-28

Applicant: Intel IP Corporation

Inventor： Sven Albers ,  Marc Dittes ,  Andreas Wolter ,  Klaus Reingruber ,  Georg Seidemann ,  Christian Geissler ,  Thomas Wagner ,  Richard Patten

IPC: G02B6/42 ,  H01L23/00

Abstract: Embodiments of the disclosure are directed to a chip package that includes a base that includes a redistribution layer; an optical transducer circuit element on the base electrically connected to the redistribution layer; an optical element adjacent to the optical transducer circuit element and at an edge of the base; and an encasement encasing the optical transducer circuit element and a portion of the optical element, wherein one side of the optical element is exposed at an edge of the encasement and at the edge of the printed circuit board.

公开(公告)号：US20180374819A1

公开(公告)日：2018-12-27

申请号：US16063145

申请日：2015-12-18

Applicant: Intel IP Corporation

Inventor： Christian Geissler ,  Sven Albers ,  Georg Seidemann ,  Andreas Wolter ,  Klaus Reingruber ,  Thomas Wagner ,  Marc Dittes

IPC: H01L23/00 ,  H01L25/065

Abstract: A method includes aligning a wire with a package body having a contact pad and moving the wire through the package body to form electrical contact with the contact pad.

公开(公告)号：US20180331080A1

公开(公告)日：2018-11-15

申请号：US15776475

申请日：2015-12-21

Applicant: Intel IP Corporation

Inventor： Christian Geissler ,  Sven Albers ,  Georg Seidemann ,  Andreas Wolter ,  Klaus Reingruber ,  Thomas Wagner ,  Marc Dittes

IPC: H01L25/16 ,  H01L23/538 ,  H01L23/498

CPC classification number: H01L25/16 ,  H01L21/568 ,  H01L23/48 ,  H01L23/49827 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/19011 ,  H01L2924/19105

Abstract: A system-in-package device includes at least three electrical device components arranged in a common package. A first electrical device component includes a first vertical dimension, a second electrical device component includes a second vertical dimension and a third electrical device component comprises a third vertical dimension. The first electrical device component and the second electrical device component are arranged side by side in the common package. Further, the third electrical device component is arranged on top of the first electrical device component in the common package. At least a part of the third electrical device component is arranged vertically between a front side level of the second electrical device component and a back side level of the second electrical device component.

公开(公告)号：US10121726B2

公开(公告)日：2018-11-06

申请号：US14839510

申请日：2015-08-28

Applicant: Intel IP Corporation

Inventor： Sven Albers ,  Klaus Reingruber ,  Andreas Wolter ,  Georg Seidemann ,  Christian Geissler ,  Alexandra Atzesdorfer ,  Sonja Koller

IPC: H01L23/373 ,  H01L23/36 ,  G06F1/20 ,  H01L23/427

Abstract: Embodiments of the present disclosure relate to a cooler for semiconductor devices. The semiconductor device may be electrically coupleable to a power source. The device may generate heat when the power source supplies power to the device during use of the device. The cooler may be coupled to one or more surfaces of the device. The cooler may include a hydrophilic material to adsorb water from ambient air. During operation of the device, the cooler may cool the device by conduction of heat away from the device to the cooler. The cooler may include water that is evaporated during use of the device to increase cooling capacity of the cooler. The cooler may be recharged with water from humidity in air when the device is not operated or operated at a lower power level. Other embodiments may be described and/or claimed.

公开(公告)号：US09865387B2

公开(公告)日：2018-01-09

申请号：US14956859

申请日：2015-12-02

Applicant: Intel IP Corporation

Inventor： Sven Albers ,  Klaus Reingruber ,  Andreas Wolter

IPC: H01F5/00 ,  H01F27/06 ,  H01F27/28 ,  H01F27/24

CPC classification number: H01F27/2804 ,  H01F27/06 ,  H01F27/24 ,  H01F2027/065 ,  H01F2027/2809

Abstract: An electronic package that includes a substrate; a first electronic component mounted on one side of the substrate; a second electronic component mounted on an opposing side of the substrate; a core mounted to the substrate, wherein the core extends through the substrate; a first wire electrically attached to at least one of the first electronic component and the substrate, wherein the first wire is wrapped around the core to form a first coil on the one side of the substrate; and a second wire electrically attached to at least one of the second electronic component and the substrate, wherein the second wire is wrapped around the core to form a second coil on the opposing side of the substrate.

公开(公告)号：US20170243815A1

公开(公告)日：2017-08-24

申请号：US15052505

申请日：2016-02-24

Applicant: Intel IP Corporation

Inventor： Klaus Reingruber ,  Sven Albers ,  Christian Geissler

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/4846 ,  H01L24/19 ,  H01L2224/04105

Abstract: Embodiments herein may relate to a package with a dielectric layer having a first face and a second face opposite the first face. A conductive line of a patterned metal redistribution layer (RDL) may be coupled with the second face of the dielectric layer. The line may include a first portion with a first width and a second portion directly coupled to the first portion, the second portion having a second width. The first portion may extend beyond a plane of the second face of the dielectric layer, and the second portion may be positioned between the first face and the second face of the dielectric layer. Other embodiments may be described and/or claimed.

公开(公告)号：US09653324B2

公开(公告)日：2017-05-16

申请号：US15182434

申请日：2016-06-14

Applicant: INTEL IP CORPORATION

Inventor： Sven Albers ,  Sonja Koller ,  Thorsten Meyer ,  Georg Seidemann ,  Christian Geissler ,  Andreas Wolter

IPC: H01L21/44 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L21/78

CPC classification number: H01L21/56 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/562 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a die having a first side and a second side disposed opposite to the first side. The IC package may further include an encapsulation material encapsulating at least a portion of the die and having a first surface that is adjacent to the first side of the die and a second surface disposed opposite to the first surface. In embodiments, the second surface may be shaped such that one or more cross-section areas of the IC package are thinner than one or more other cross-section areas of the IC package. Other embodiments may be described and/or claimed.

公开(公告)号：US20160293453A1

公开(公告)日：2016-10-06

申请号：US15182434

申请日：2016-06-14

Applicant: INTEL IP CORPORATION

Inventor： Sven Albers ,  Sonja Koller ,  Thorsten Meyer ,  Georg Seidemann ,  Christian Geissler ,  Andreas Wolter

IPC: H01L21/56 ,  H01L23/00 ,  H01L21/78 ,  H01L23/31

CPC classification number: H01L21/56 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/562 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a die having a first side and a second side disposed opposite to the first side. The IC package may further include an encapsulation material encapsulating at least a portion of the die and having a first surface that is adjacent to the first side of the die and a second surface disposed opposite to the first surface. In embodiments, the second surface may be shaped such that one or more cross-section areas of the IC package are thinner than one or more other cross-section areas of the IC package. Other embodiments may be described and/or claimed.

公开(公告)号：US10816742B2

公开(公告)日：2020-10-27

申请号：US16182450

申请日：2018-11-06

Applicant: Intel IP Corporation

Inventor： Georg Seidemann ,  Christian Geissler ,  Sven Albers ,  Thomas Wagner ,  Marc Dittes ,  Klaus Reingruber ,  Andreas Wolter ,  Richard Patten

IPC: G02B6/42 ,  G02B6/122 ,  G02B6/132 ,  G02B6/30 ,  G02B6/12 ,  G02B6/43

Abstract: Disclosed is a package comprising a substrate having a patterned surface with an optical contact area, an optical redistribution layer (oRDL) feature, and a build-up material extending over the patterned surface of the substrate and around portions of the oRDL features. In some embodiments, the package comprises a liner sheathing the oRDL features. In some embodiments, the oRDL feature extends through openings in an outer surface of the build-up material and forms posts extending outward from the outer surface. In some embodiments, the package comprises an electrical redistribution layer (eRDL) feature, at least some portion of which overlap at least some portion of the oRDL feature. In some embodiments, the package comprises an optical fiber coupled to the oRDL features.

公开(公告)号：US10411000B2

公开(公告)日：2019-09-10

申请号：US15087477

申请日：2016-03-31

Applicant: Intel IP Corporation

Inventor： Marc Stephan Dittes ,  Sven Albers ,  Christian Georg Geissler ,  Andreas Wolter ,  Klaus Reingruber ,  Georg Seidemann ,  Thomas Wagner ,  Richard Patten

IPC: F21V15/00 ,  H01L25/16 ,  H01L23/31

Abstract: A microelectronic package is described with an illuminated backside exterior. In one example, the package has a package substrate, a die attached to the package substrate, a cover over the die and the package substrate, a lamp, and a screen over the die, externally visible and optically coupled to the lamp so that when the lamp is illuminated the illumination is externally visible through the screen.