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    CACHE LINE COMPACTION OF COMPRESSED DATA SEGMENTS
    11.
    发明公开
    CACHE LINE COMPACTION OF COMPRESSED DATA SEGMENTS 有权
    压缩数据段的缓存线压缩

    公开(公告)号：EP3178005A1

    公开(公告)日：2017-06-14

    申请号：EP15742447.4

    申请日：2015-07-09

    Applicant: Qualcomm Incorporated

    Inventor： TURNER, Andrew Edmund ,  PATSILARAS, George ,  RYCHLIK, Bohuslav

    IPC: G06F12/08

    CPC classification number: G06F12/0875 ,  G06F12/0802 ,  G06F12/0886 ,  G06F2212/1021 ,  G06F2212/401 ,  G06F2212/45 ,  G06F2212/608

    Abstract: Methods, devices, and non-transitory process-readable storage media for compacting data within cache lines of a cache. An aspect method may include identifying, by a processor of the computing device, a base address (e.g., a physical or virtual cache address) for a first data segment, identifying a data size (e.g., based on a compression ratio) for the first data segment, obtaining a base offset based on the identified data size and the base address of the first data segment, and calculating an offset address by offsetting the base address with the obtained base offset, wherein the calculated offset address is associated with a second data segment. In some aspects, the method may include identifying a parity value for the first data segment based on the base address and obtaining the base offset by performing a lookup on a stored table using the identified data size and identified parity value.

    Abstract translation: 用于压缩高速缓存的高速缓存行内的数据的方法，设备和非瞬态过程可读存储介质。 方面方法可以包括由计算设备的处理器识别第一数据段的基地址（例如，物理或虚拟高速缓存地址），识别第一数据段的数据大小（例如，基于压缩比） 数据段，基于所识别的数据大小和第一数据段的基地址获得基础偏移量，以及通过用所获得的基础偏移量偏移基础地址来计算偏移地址，其中计算出的偏移地址与第二数据相关联 分割。 在一些方面中，该方法可以包括基于基地址识别第一数据段的奇偶校验值，并且通过使用识别的数据大小和识别的奇偶校验值在存储的表上执行查找来获得基准偏移量。

    SUPPLEMENTAL WRITE CACHE COMMAND FOR BANDWIDTH COMPRESSION
    15.
    发明申请
    SUPPLEMENTAL WRITE CACHE COMMAND FOR BANDWIDTH COMPRESSION 审中-公开
    用于带宽压缩的补充写缓存命令

    公开(公告)号：WO2016028439A1

    公开(公告)日：2016-02-25

    申请号：PCT/US2015/042081

    申请日：2015-07-24

    Applicant: QUALCOMM INCORPORATED

    Inventor： TURNER, Andrew Edmund ,  PATSILARAS, George ,  RYCHLIK, Bohuslav

    IPC: G06F12/08

    CPC classification number: G06F12/0893 ,  G06F12/0866 ,  G06F12/0886 ,  G06F2212/1028 ,  G06F2212/1044 ,  G06F2212/401 ,  Y02D10/13

    Abstract: Aspects include computing devices, systems, and methods for implementing a cache memory access requests for data smaller than a cache line and eliminating overfetching from a main memory by writing supplemental data to the unfilled portions of the cache line. A cache memory controller may receive a cache memory access request with a supplemental write command for data smaller than a cache line. The cache memory controller may write supplemental to the portions of the cache line not filled by the data in response to a write cache memory access request or a cache miss during a read cache memory access request. In the event of a cache miss, the cache memory controller may retrieve the data from the main memory, excluding any overfetch data, and write the data and the supplemental data to the cache line. Eliminating overfetching reduces bandwidth and power required to retrieved data from main memory.

    Abstract translation: 方面包括用于对小于高速缓存线的数据实现高速缓冲存储器访问请求的计算设备，系统和方法，并且通过将补充数据写入到高速缓存行的未填充部分来消除从主存储器的超时。 高速缓存存储器控制器可以接收具有小于高速缓存线的数据的补充写入命令的高速缓存存储器访问请求。 高速缓冲存储器控制器可以在读取高速缓存存储器访问请求期间响应于写入高速缓存存储器访问请求或高速缓存未命中而对未被数据填充的高速缓存行的部分进行补充。 在高速缓存未命中的情况下，高速缓存存储器控制器可以从主存储器检索数据，排除任何过采取数据，并将数据和补充数据写入高速缓存行。 消除过载减少从主存储器检索数据所需的带宽和功率。

    CACHE LINE COMPACTION OF COMPRESSED DATA SEGMENTS
    16.
    发明申请
    CACHE LINE COMPACTION OF COMPRESSED DATA SEGMENTS 审中-公开
    压缩数据段的缓存行压缩

    公开(公告)号：WO2016022247A1

    公开(公告)日：2016-02-11

    申请号：PCT/US2015/039736

    申请日：2015-07-09

    Applicant: QUALCOMM INCORPORATED

    Inventor： TURNER, Andrew Edmund ,  PATSILARAS, George ,  RYCHLIK, Bohuslav

    IPC: G06F12/08

    CPC classification number: G06F12/0875 ,  G06F12/0802 ,  G06F12/0886 ,  G06F2212/1021 ,  G06F2212/401 ,  G06F2212/45 ,  G06F2212/608

    Abstract: Methods, devices, and non-transitory process-readable storage media for compacting data within cache lines of a cache. An aspect method may include identifying, by a processor of the computing device, a base address (e.g., a physical or virtual cache address) for a first data segment, identifying a data size (e.g., based on a compression ratio) for the first data segment, obtaining a base offset based on the identified data size and the base address of the first data segment, and calculating an offset address by offsetting the base address with the obtained base offset, wherein the calculated offset address is associated with a second data segment. In some aspects, the method may include identifying a parity value for the first data segment based on the base address and obtaining the base offset by performing a lookup on a stored table using the identified data size and identified parity value.

    Abstract translation: 用于在高速缓存的高速缓存行中压缩数据的方法，设备和非暂态过程可读存储介质。 方面方法可以包括由计算设备的处理器识别用于第一数据段的基地址（例如，物理或虚拟高速缓存地址），识别第一数据段的数据大小（例如，基于压缩比） 数据段，基于所识别的数据大小和第一数据段的基址获得基本偏移，并且通过利用所获得的基本偏移量偏移基址来计算偏移地址，其中所计算的偏移地址与第二数据相关联 分割。 在一些方面，所述方法可以包括基于所述基地址识别所述第一数据段的奇偶校验值，并通过使用所识别的数据大小和所识别的奇偶校验值对存储的表执行查找来获得所述基本偏移。

    METHOD AND APPARATUS FOR A SHARED CACHE WITH DYNAMIC PARTITIONING
    17.
    发明申请
    METHOD AND APPARATUS FOR A SHARED CACHE WITH DYNAMIC PARTITIONING 审中-公开
    用于具有动态分区的共享缓存的方法和装置

    公开(公告)号：WO2016010705A1

    公开(公告)日：2016-01-21

    申请号：PCT/US2015/037670

    申请日：2015-06-25

    Applicant: QUALCOMM INCORPORATED

    Inventor： PALACHARLA, Subbarao ,  KHAN, Moinul ,  ARTIERI, Alain ,  BHOLE, Kedar ,  CHAMARTY, Vinod ,  LI, Yanru ,  SANKURATRI, Raghu ,  PATSILARAS, George ,  THIRUNAGARI, Pavan Kumar ,  TURNER, Andrew Edmund ,  WOO, Jeong-Ho

    IPC: G06F12/08 ,  G06F9/50

    CPC classification number: G06F12/0893 ,  G06F9/50 ,  G06F12/084 ,  G06F12/0895 ,  G06F2212/1044 ,  G06F2212/152 ,  G06F2212/601 ,  G06F2212/6042 ,  Y02D10/13

    Abstract: Aspects include computing devices, systems, and methods for dynamically partitioning a system cache by sets and ways into component caches. A system cache memory controller may manage the component caches and manage access to the component caches. The system cache memory controller may receive system cache access requests and reserve locations in the system cache corresponding to the component caches correlated with component cache identifiers of the requests. Reserving locations in the system cache may activate the locations in the system cache for use by a requesting client, and may also prevent other client from using the reserved locations in the system cache. Releasing the locations in the system cache may deactivate the locations in the system cache and allow other clients to use them. A client reserving locations in the system cache may change the amount of locations it has reserved within its component cache.

    Abstract translation: 方面包括计算设备，系统和方法，用于通过集合和方式动态地将系统缓存分区到组件高速缓存中。 系统高速缓冲存储器控制器可以管理组件高速缓存并管理对组件高速缓存的访问。 系统高速缓冲存储器控制器可以接收系统高速缓存访​​问请求，并且在系统高速缓存中保留对应于与请求的组件高速缓存标识符相关联的组件高速缓存的位 在系统缓存中预留位置可以激活系统高速缓存中的位置以供请求客户端使用，并且还可以防止其他客户端使用系统高速缓存中的保留位置。 释放系统缓存中的位置可以停用系统缓存中的位置，并允许其他客户端使用它们。 保留系统缓存中的位置的客户端可以改变其在其组件高速缓存中保留的位置的数量。

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