Abstract:
A microelectronic processing component can include a substrate and a corrosion-resistant layer. The substrate can include a metal-containing material, and the corrosion-resistant layer can be adjacent to the surface region. The corrosion-resistant layer can include a first portion and a second portion each including a rare earth compound, wherein the first portion is disposed between the substrate and the second portion, and the first portion has a first porosity, and the second portion has a second porosity that is greater than the first porosity. The component can be component within a processing apparatus used to process microelectronic work pieces. In a particular embodiment, the component can be exposed to the processing conditions as seen by the microelectronic workpiece when fabrication a microelectronic device from the microelectronic workpiece. Methods can be used to achieve the difference in porosity, and such methods can be for articles other than microelectronic processing components.
Abstract:
A processing device includes a plurality of walls defining an interior space configured to be exposed to plasma and a surface coating on the interior surface of at least one of the plurality of walls. The surface coating includes pores forming interconnected porosity. The processing device further includes a sealant residing in at least a portion of the pores of the surface coating. In an embodiment, the sealant can be a thermally cured sealant having a cure temperature not greater than about 100C. In another embodiment, the sealant can be an epoxy sealant having a viscosity of not greater than 500 cP in liquid precursor form. In yet another embodiment, the sealant can be a low shrinkage sealant characterized by a solidification shrinkage of not greater than 8%.
Abstract:
An electrostatic chuck is disclosed which includes a substrate, a patterned conductive layer overlying the substrate, such that the patterned conductive layer is defining electrode pathways separated by gaps. The electrostatic chuck also includes a resistive layer overlying the patterned conductive layer and a low-k dielectric layer overlying the substrate and disposed in the gaps between the electrode pathways. The low-k dielectric layer includes a material having a different phase than the material of the substrate.
Abstract:
This invention relates to a dense ceramics having ESD dissipative characteristics, tunable volume and surface resistivies in semi-insulative range (10 - 10 Ohm-cm), substantially pore free, high flexural strength, light colors, for desired ESD dissipation characteristics, structural reliability, high vision recognition, low wear and particulate contamination to be used as ESD dissipating tools, fixtures, load bearing elements, work surfaces, containers in manufacturing and assembling electrostatically sensitive microelectronic, electromagnetic, electro-optic components, devices and systems.
Abstract:
A sapphire substrate includes a generally planar surface having a crystallographic orientation selected from the group consisting of a-plane, r-plane, m-plane, and c-plane orientations, and having a nTTV of not greater than about 0.037 µm/cm 2 , wherein nTTV is total thickness variation normalized for surface area of teh generally planar surface, the substrate having a diameter not less than about 9.0 cm.
Abstract translation:蓝宝石衬底包括具有选自由a面,r面,m面和c面取向组成的组的结晶取向,且具有不大于约0.037μm/ cm 2的nTTV的大致平坦的表面, SUP> 2,其中nTTV是对于大致平坦表面的表面积归一化的总厚度变化,所述基底具有不小于约9.0cm的直径。
Abstract:
A Coulombic electrostatic chuck is disclosed which includes a substrate, a conductive layer overlying the substrate, and an arc elimination layer overlying the conductive layer. The electrostatic chuck further includes a high-k dielectric layer overlying the arc elimination layer, wherein the high-k dielectric layer has a dielectric constant of not less than about 10 and a resistivity of not less than about 1011 Ohm-cm.
Abstract:
A semiconductor processing component includes a substrate and a layer overlying the substrate. The layer has a composition ReA y O 1.5+2y , wherein Re is Y, La, a Lanthanoid series element, or a combination thereof, A is (Si 1-a Ge a ), 0.25 y 1.2, and 0 a 1.
Abstract translation:半导体处理部件包括衬底和覆盖衬底的层。 该层具有组成,其中Re是Y,La,镧系元素,或它们的组合,A是(Si < 1-a sub> a sub>),0.25y 1.2和0 a 1。
Abstract:
ESD safe ceramic component is provided which includes a sintered composition which is formed of a base material and a resistivity modifier. The base material includes a primary component and a secondary component, the primary component including Al2O3 and the secondary component including tetragonal-ZrO2.
Abstract translation:提供ESD安全陶瓷部件,其包括由基础材料和电阻率调节剂形成的烧结组合物。 基材包括主要组分和次要组分,主要组分包括Al 2 O 3,次要组分包括四方晶ZrO 2。
Abstract:
A structural component is provided that includes a substrate and a ceramic layer deposited thereon. The ceramic layer is formed of a ceramic electrostatic discharge dissipative material and has an electrical resistivity within a range of about 10 to about 10 ohm-cm.