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11.发明专利
公开(公告)号：JP2003022629A
公开(公告)日：2003-01-24
申请号：JP2001208349
申请日：2001-07-09
Inventor： HIRASAWA YUJI , OKAMOTO ICHIRO
Abstract: PROBLEM TO BE SOLVED: To provide a digital signal reproducing device and digital signal reproducing method capable of improving the ability to acquire data of block units.
SOLUTION: The digital signal reproducing device adds and records synchronizing signals, addresses and parities for error correction for every block unit in recording the data to a recording medium and reproduces the data by identifying the block units on the basis of the synchronizing signal and addresses in reproducing and correcting the errors by using the parities. The digital signal reproducing device described above is provided with an ECC first time 2 to perform a first error correction by using the parities, an ID interpolation 3 to interpolates the addresses and an ECC second time 4 to perform a second error correction using the parities after the interpolation.
COPYRIGHT: (C)2003,JPOAbstract translation: 要解决的问题：提供能够提高获取块单元的数据的能力的数字信号再现装置和数字信号再现方法。 解决方案：数字信号再现装置在将数据记录到记录介质时，对每个块单元添加和记录用于纠错的同步信号，地址和奇偶校验，并且通过基于同步信号和地址来识别块单元来再现数据 通过使用奇偶校验来再现和纠正错误。 上述数字信号再现装置具有ECC第一时间2，以通过使用奇偶校验执行第一纠错，ID插值3内插地址和ECC第二时间4，以使用之后的奇偶校验执行第二纠错 插值。
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公开(公告)号：JPH11341306A
公开(公告)日：1999-12-10
申请号：JP14340598
申请日：1998-05-25
Applicant: SONY CORP
Inventor： OKAMOTO ICHIRO , YAMAMURA TAKAYA , KOTANI YASUTAKA , YOSHIOKA SHINGO
Abstract: PROBLEM TO BE SOLVED: To reduce response time until a PLL is locked and also to reduce the scale of a circuit. SOLUTION: This digital PLL circuit, which produces an output signal of a frequency nfref by making the frequency fref of a reference input signal n times, has a 1st loop provided with an analog phase comparing means 6 which performs phase comparison of the reference pilot signal of a frequency f/m that is externally supplied with the feedback pilot signal of a frequency, that undergoes m frequency division of an output signal by a variable frequency dividing means 5 and controls the frequency of the output signal and a 2nd loop, which is provided with a digital frequency comparing means 2 that counts an output signal in each cycle of the reference input signal and produces a difference with the (n) as a stage number and a noise shaper 4 which integrates the stage number and calculates it for every cycle of the feedback pilot signal and controls the frequency of the output signal by changing the frequency division ratio of the means 5 of a 1st loop through the shaper 4.
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公开(公告)号：JPH11102578A
公开(公告)日：1999-04-13
申请号：JP26454197
申请日：1997-09-29
Applicant: SONY CORP
Inventor： SATO NAOYUKI , KOTANI YASUTAKA , OKAMOTO ICHIRO
IPC: G11B20/14
Abstract: PROBLEM TO BE SOLVED: To enable adjustment of clocks for all used frequencies and obtain a good bit error rate even in the presence of irregular characteristics of an LPF and a PLL, in a reproduction signal processing circuit provided with an analog/digital conversion means, which digitizes input signals as reproduction signals of digital data in accordance with a clock signal generated on the basis of the input signals by a clock signal generation means. SOLUTION: A control part 20 which controls a clock signal generation part 7 to adjust by an EVR 30 the phase of a clock signal to be fed to an A/D converter 6 on the basis of a phase error ER obtained by a phase error detection circuit 10 set at a letter stage of the A/D converter 6, is provided. A circuit characteristic change of the clock signal generation part 7 and a characteristic change of an LPF set on the former stage side than the A/D converter 6 are absorbed by the adjustment of the phase of the clock signal.
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公开(公告)号：JPH06165120A
公开(公告)日：1994-06-10
申请号：JP33803692
申请日：1992-11-25
Applicant: SONY CORP
Inventor： YOSHIHIRO TOSHITAKA , OKADA HIROSHI , OKAMOTO ICHIRO , INOUE HAJIME
Abstract: PURPOSE:To attain error correction using a product code even at the time of slow reproduction in a digital VTR. CONSTITUTION:A video signal to which a parity constituted of a project code to be completed in each track is added is recorded in a magnetic tape (not shown). A slow reproducing speed is set up to 1/odd number and reproduced digital video signals are stored in three bank memories M1 to M3 having storage capacity corresponding to one track. Since one track is scanned plural times at the time of slow reproduction, all reproduced signals for one track can be stored. Therefore error correction using a product code can be attained only by reading out the contents of the memories M1 to M3 and supplying the read contents to an ECC 11 and picture quality can be prevented from being deteriorated.
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公开(公告)号：JPH06119719A
公开(公告)日：1994-04-28
申请号：JP7906393
申请日：1993-03-12
Applicant: SONY CORP
Inventor： INOUE HAJIME , OKAMOTO ICHIRO , OGURO MASAKI , KANOTA KEIJI , KUBOTA YUKIO
IPC: G11B20/12
Abstract: PURPOSE:To record video data without being influenced by a vibration of a magnetic tape to be generated immediately after a magnetic head is brought into contact with the magnetic tape. CONSTITUTION:A track on the magnetic tape is formed with an ATF area, an audio data recording area AUDIO, a video data recording area VIDEO, a subcode recording area SUBCODE and an ATF recording area in order in the direction from commencing the contact of the magnetic head H. Audio data not processed of compression is recorded in the audio data recording area, while video data processed of compression and audio data processed of compression are recorded in the video data recording area.
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Patent Agency Ranking
公开(公告)号：JPH05174552A
公开(公告)日：1993-07-13
申请号：JP34303191
申请日：1991-12-25
Applicant: SONY CORP
Inventor： YAMASHITA KEITARO , OKAMOTO ICHIRO , KOMAZAKI TAKAHIRO
IPC: G11B5/027 , G11B15/087 , G11B27/029 , G11B27/036 , G11B27/28
Abstract: PURPOSE:To prevent that a discontinuous part of voice signals generated when the signals are coupled and dubbed is output as noises. CONSTITUTION:In dubbing voice signals, a dubbing starting data '1' generated in an ID generating circuit 6 is recorded in an index area of, e.g. four fields, and the voice signals are recorded from the next track. In order to reproduce the dubbed voice recorded in the above manner, first, the dubbing starting data is detected by an ID register 25 and supplied to a system controller 8 to judge whether the voice is dubbed or not. If the voice is the dubbed one, a muting instruction is generated to mute circuits 30A-30D, and the voice signals to be reproduced are muted for a predetermined time, e.g. four fields. Accordingly, discontinuous signals remaining at the coupling part of the voice signals are prevented from being output as noises.
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17.发明专利
公开(公告)号：JP2003166849A
公开(公告)日：2003-06-13
申请号：JP2001368470
申请日：2001-12-03
Applicant: SONY CORP
Inventor： KATAOKA MASAKI , NAKADA SHINGO , OKAMOTO ICHIRO , HIDAI TAKESHI
Abstract: PROBLEM TO BE SOLVED: To provide a mobile communication apparatus, a position information providing device and a position information providing system capable of selecting an apparatus meeting with a predetermined condition among a plurality of mobile communication apparatuses existing in a same area and capable of easily identifying a direction and a distance with respect to the selected counterpart apparatus in a system for performing navigation between the mobile communication apparatuses. SOLUTION: This position information providing system is constituted by the mobile communication apparatus and the position information providing device. When the mobile communication apparatus accesses the position information providing device, the position information providing device detects the position information of the mobile communication apparatus and the area is determined. The position information of other communication apparatuses existing in the same area is transmitted to the communication apparatus, and the desired communication apparatus is selected based on the information. The navigation is started by consent of both sides. In the respective communication apparatuses, the direction and the distance with respect to the counterpart communication apparatus are automatically calculated based on the direction information to which the own communication apparatus moves, own position information showing a present position, and position information of the counterpart apparatus. The direction to the counterpart apparatus is displayed on a display part with an arrow. COPYRIGHT: (C)2003,JPO
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公开(公告)号：JP2001119272A
公开(公告)日：2001-04-27
申请号：JP29592999
申请日：1999-10-18
Applicant: SONY CORP
Inventor： YAMAOKA SHINSUKE , OKAMOTO ICHIRO , SAITO TAKEHIKO , KOTANI YASUTAKA , NIKATA KENJI
Abstract: PROBLEM TO BE SOLVED: To reduce the production cost of a digital LSI(large scale integrated circuit), for example, by generating an oscillation signal without converting a digital signal into an analog signal. SOLUTION: This device is provided with a delay coarse adjustment circuit 3 which has its delay value that is changed stepwise according to a delay coarse adjustment signal S11 and gives rough delay to an inputted oscillation signal S12, a delay fine adjustment circuit 4 which has its delay value that is changed stepwise according to a delay fine adjustment signal S2 and gives fine delay smaller than the delay value of the circuit 3 to an inputted oscillation signal S13 and an inverter circuit 5 to which an oscillation signal S14 is inputted from the circuit 3 or 4. In such an arrangement, the highly accurate delay is secured to generate an oscillation output signal S15 by carrying out the fine adjustment of delay via the circuit 3 and also carrying out the fine adjustment of delay via the circuit 4. When the circuits 3, 4 and 5 are connected together in a ring form, the oscillation frequency of oscillation signals can be controlled stepwise.
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公开(公告)号：JPH11328855A
公开(公告)日：1999-11-30
申请号：JP13395998
申请日：1998-05-15
Applicant: SONY CORP
Inventor： SATO NAOYUKI , KOTANI YASUTAKA , OKAMOTO ICHIRO
IPC: G11B20/10
Abstract: PROBLEM TO BE SOLVED: To provide method and device for adjusting automatic gain control and a decoding circuit eliminating limitation of the degree of freedom in a manufacturing line and facilitating reajustment when an adjustment value is shifted by some cause after assembling to a set. SOLUTION: A ternary detection part 20 detects ternary from an equalization output from a conversion circuit 19. A sample extraction part 21 absolutizes a sample incorporated in one among the ternary detected by the ternary detection part 20 to extract it. An integrator 22 integrates the sample extracted by the sample extraction part 21. A CPU 23 generates an envelope control signal based on the integrated value from the integrator 22. An envelope adjustment part 24 controls a gain of an AGC based on the envelope control signal from the CPU 23.
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公开(公告)号：JPH1173741A
公开(公告)日：1999-03-16
申请号：JP23364897
申请日：1997-08-29
Applicant: SONY CORP
Inventor： KOTANI YASUTAKA , OKAMOTO ICHIRO , YOSHIOKA SHINGO
IPC: G11B20/14
Abstract: PROBLEM TO BE SOLVED: To shorten the time required for pulling-in PLL at the time when the next data is reproduced by supplying dummy signals to the PLL and lock it while the playback data is not present. SOLUTION: An edge pulse is outputted by an edge pulse generating circuit 21 based on a switch pulse(SWP) signal to be supplied to a counter 22. This edge pulse is counted by the counter 22 to supply counts to a decoder 23. In response to the number of counts, PLLSW signals and enb10M signals outputted from the decoder 23 are activated. The enb10M signals are supplied to a selector 25, and in response to enb10M signals recording signals supplied to the selector 25 and clock signals whose frequency is divided to 1/4 in a 1/4 frequency dividing circuit 24 are switched to be supplied to the PLL circuit of the next RF system.
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