公开(公告)号：FR2845522A1

公开(公告)日：2004-04-09

申请号：FR0212278

申请日：2002-10-03

Applicant: ST MICROELECTRONICS SA

Inventor： MARTY MICHEL ,  CORONEL PHILIPPE ,  LEVERD FRANCOIS

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/08 ,  H01L29/417 ,  H01L29/732 ,  H01L21/74

Abstract: An integrated circuit incorporates a buried layer of the type with conductivity determined in a plane essentially parallel to a plane of a main surface of the circuit. The median part of this buried layer (23, 24) is filled with a metallic type material (29). An Independent claim is also included for a method for the formation of a layer buried in a semiconductor substrate of an integrated circuit.

公开(公告)号：FR2811473A1

公开(公告)日：2002-01-11

申请号：FR0008686

申请日：2000-07-04

Applicant: ST MICROELECTRONICS SA

Inventor： MARTY MICHEL ,  BAUDRY HELENE ,  LEVERD FRANCOIS

IPC: H01L21/316 ,  H01L21/762 ,  H01L21/763 ,  H01L21/331 ,  H01L21/306

Abstract: Prior to the implementation of transistors, one configures within the substrate a deep insulated drain following the configuration within the substrate of a less deep insulated drain lengthening the deep drain. The configuration of the deep drain includes a coating of the internal walls of the drain by an initial layer of oxide (100) obtained by a rapid thermal oxidation and a filling of the drain with polysilicon (120) inside an envelope formed with an insulating material (101). The configuration of the less deep drain also includes a coating of the internal walls with an initial oxide layer (15) obtained by rapid thermal oxidation and a filling with an insulating material (16, 17). An Independent claim is also included for an integrated circuit incorporating within a substrate some insulating deep drain and less deep drain regions separating the transistors.

公开(公告)号：FR2894066A1

公开(公告)日：2007-06-01

申请号：FR0512159

申请日：2005-11-30

Applicant: ST MICROELECTRONICS SA ,  STMICROELECTRONICS CROLLES SAS

Inventor： BAJOLET AURELIE ,  GIRAUDIN JEAN CHRISTOPHE ,  LEVERD FRANCOIS

IPC: H01L21/02 ,  H01L27/108

Abstract: Le procédé comprend une phase de réalisation de tranchées et une phase de formation des éléments (8, 9, 10) du condensateur (CD) dans la tranchée correspondante. La phase de réalisation des tranchées comprend une succession de cycles qui comprennent chacun une gravure plasma et une passivation par plasma. La phase de formation des éléments (8, 9, 10) du condensateur (CD) dans la tranchée comprend un dépôt conforme sur les parois de la tranchée, et de manière préférentielle se fait par dépôt par couches atomiques.

公开(公告)号：FR2848724B1

公开(公告)日：2005-04-15

申请号：FR0215837

申请日：2002-12-13

Applicant: ST MICROELECTRONICS SA

Inventor： MARTY MICHEL ,  LEVERD FRANCOIS ,  CORONEL PHILIPPE

IPC: H01L21/68 ,  H01L21/762 ,  H01L21/768 ,  H01L21/84 ,  H01L23/48 ,  H01L27/12 ,  H01L23/535

Abstract: The production of connections buried in an integrated circuit comprises: (a) providing a structure made up of a first support slice stuck in the rear surface of a thin semiconductor slice, one or more integrated circuit elements possibly being realised in or above the thin slice; (b) sticking a second support slice on the structure at the side of the leading surface of the thin slice; (c) eliminating the first support slice; (d) forming some connections between the different zones of the rear surface of the thin slice; (e) sticking a third support slice on the connections; and (f) eliminating the second support slice. An Independent claim is also included for an integrated circuit incorporating some components and produced by the above process.

公开(公告)号：FR2848724A1

公开(公告)日：2004-06-18

申请号：FR0215837

申请日：2002-12-13

Applicant: ST MICROELECTRONICS SA

Inventor： MARTY MICHEL ,  LEVERD FRANCOIS ,  CORONEL PHILIPPE

IPC: H01L21/68 ,  H01L21/762 ,  H01L21/768 ,  H01L21/84 ,  H01L23/48 ,  H01L27/12 ,  H01L23/535

Abstract: The production of connections buried in an integrated circuit comprises: (a) providing a structure made up of a first support slice stuck in the rear surface of a thin semiconductor slice, one or more integrated circuit elements possibly being realised in or above the thin slice; (b) sticking a second support slice on the structure at the side of the leading surface of the thin slice; (c) eliminating the first support slice; (d) forming some connections between the different zones of the rear surface of the thin slice; (e) sticking a third support slice on the connections; and (f) eliminating the second support slice. An Independent claim is also included for an integrated circuit incorporating some components and produced by the above process.

公开(公告)号：FR2811473B1

公开(公告)日：2003-09-05

申请号：FR0008686

申请日：2000-07-04

Applicant: ST MICROELECTRONICS SA

Inventor： MARTY MICHEL ,  BAUDRY HELENE ,  LEVERD FRANCOIS

IPC: H01L21/316 ,  H01L21/762 ,  H01L21/763 ,  H01L21/331 ,  H01L21/306

Abstract: Prior to the implementation of transistors, one configures within the substrate a deep insulated drain following the configuration within the substrate of a less deep insulated drain lengthening the deep drain. The configuration of the deep drain includes a coating of the internal walls of the drain by an initial layer of oxide (100) obtained by a rapid thermal oxidation and a filling of the drain with polysilicon (120) inside an envelope formed with an insulating material (101). The configuration of the less deep drain also includes a coating of the internal walls with an initial oxide layer (15) obtained by rapid thermal oxidation and a filling with an insulating material (16, 17). An Independent claim is also included for an integrated circuit incorporating within a substrate some insulating deep drain and less deep drain regions separating the transistors.

公开(公告)号：FR2838866A1

公开(公告)日：2003-10-24

申请号：FR0205073

申请日：2002-04-23

Applicant: ST MICROELECTRONICS SA

Inventor： CORONEL PHILIPPE ,  LEVERD FRANCOIS ,  SKOTNICKI THOMAS

IPC: H01L21/02 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/68 ,  H01L21/762 ,  H01L21/8242 ,  H01L23/544 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L51/00 ,  H01L51/40 ,  H01L21/70 ,  H01L27/108

Abstract: Fabrication of an integrated electronic component comprises: producing an initial structure (SI) incorporating volumes of respective materials forming a definite pattern (M) on a first substrate; transferring the pattern to a second substrate (200); and producing, on the second substrate surface, an additional structure by using the volumes of the materials of the pattern as alignment markers. Fabrication of an integrated electronic component comprises: (a) producing, on the surface of a first substrate (100), an initial structure (SI) incorporating volumes of respective materials, at least part of the volumes forming a definite pattern (M); (b) transferring at least a part of the initial structure (SI) comprising the pattern of the first substrate (100) to a second substrate (200); and (c) producing, on the surface of the second substrate (200), an additional structure by using at least some of the volumes of the materials of the pattern (M) as alignment markers. Independent claims are given for: (i) an integrated electronic component obtained by the invented process; and (ii) an electronic device comprising a transistor, or a diode, or a dynamic random access memory (DRAM) element.

公开(公告)号：FR2830984A1

公开(公告)日：2003-04-18

申请号：FR0113375

申请日：2001-10-17

Applicant: ST MICROELECTRONICS SA

Inventor： MARTY MICHEL ,  LEVERD FRANCOIS ,  CORONEL PHILIPPE ,  TORRES JOAQUIM

IPC: H01L21/762 ,  H01L21/764

公开(公告)号：FR2821208B1

公开(公告)日：2003-04-11

申请号：FR0102347

申请日：2001-02-21

Applicant: ST MICROELECTRONICS SA

Inventor： CORONEL PHILIPPE ,  LEVERD FRANCOIS ,  FERREIRA PAUL

IPC: H01L21/60 ,  H01L21/768 ,  H01L23/52 ,  H01L21/8239

Abstract: The invention relates to a process for protection of the grid of a transistor in an integrated circuit for production of a local interconnection pad straddling over the grid and the silicon substrate on which it is formed. The process consists of applying a double dielectric-conducting layer on the transistor grid into which a polysilicon layer is added in order to use the selectivity principle, which is large considering the etching of polysilicon with respect to the oxide in which the local interconnection pad is formed. Furthermore, with the process according to the invention, a silicidation treatment can be applied beforehand on the active areas of the transistor and the grid.

公开(公告)号：FR2819633A1

公开(公告)日：2002-07-19

申请号：FR0100691

申请日：2001-01-18

Applicant: ST MICROELECTRONICS SA

Inventor： CORONEL PHILIPPE ,  PIAZZA MARC ,  LEVERD FRANCOIS

IPC: H01L21/8242 ,  H01L27/108

Abstract: A method for the integration of a Dynamic Random Access Memory (DRAM), allowing a freedom from the alignment margins inherent in the photoengraving of the upper electrode for the contact passage of the bit line, the retreat of the upper electrode being auto-aligned on the lower electrode, consists of: (a) forming a topographical difference at the spot (A) where the opening for the upper electrode is to be realised; (b) depositing a layer of non-doped polysilicon on the upper electrode; (c) producing an implantation of strongly inclined doping in this layer; (d) selectively engraving the non-doped part of the layer situated in the lower part of the zone (A) presenting the topographical difference; (e) and engraving the remaining part of the polysilicon layer as well as the upper electrode layer situated in the lower part.