公开(公告)号：FR2838237A1

公开(公告)日：2003-10-10

申请号：FR0204165

申请日：2002-04-03

Applicant: ST MICROELECTRONICS SA

Inventor： SKOTNICKI THOMAS ,  BENSAHEL DANIEL

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/786 ,  H01L27/105

Abstract: The transistor (T) is situated above a base layer (1) formed on a semiconductor substrate (SB) of a relaxed silicon-germanium alloy, and comprises under the insulated gate (7) a first constrained silicon layer (2) rested on the base layer (1), a buried insulator layer (10) and a second constrained silicon layer (4) extending between the regions of the source (S) and the drain (D) of the transistor. The thickness of the two constrained silicon layers (2,4) and that of the intermediate insulator layer (10) is much less than that of the base layer, and it is a few tens of nanometres, for example 20 nm. The thickness of the base layer (1) is of the order of a few micrometres, for example 2 micrometres. The manufacturing method comprises the formation of the base layer (1) on the silicon substrate (SB), the first constrained silicon layer (2), an intermediate layer of silicon-germanium, the second constrained silicon layer (4), the insulated gate (7) of the transistor flanked by insulating regions (8), an etching of the intermediate layer so to form a tunnel below the insulated gate, filling the tunnel with an insulator material (10), and the formation of the regions of the source (S) and the drain (D). The two constrained silicon layers (2,4) and the intermediate layer are formed by non-selective epitaxy, and an isolation zone (5) is formed in upper part of the base layer compatible with non-relaxation of constraints in the constrained silicon layers.

公开(公告)号：FR2812763A1

公开(公告)日：2002-02-08

申请号：FR0010346

申请日：2000-08-04

Applicant: ST MICROELECTRONICS SA

Inventor： BENSAHEL DANIEL ,  KERMARREC OLIVIER ,  CAMPIDELLI YVES

IPC: H01L21/20 ,  H01L29/12 ,  H01L33/00 ,  H01L33/06 ,  H01L21/205

Abstract: Formation of quantum dots (41) on a monocrystalline semiconductor substrate (40) involves gas-phase epitaxy of the quantum dot material on the substrate under optimum growth conditions to ensure growth at a controllable maximum rate. In an initial stage, quantum dot material gas is blown onto the substrate to provide a deposition rate distinctly higher than the controllable maximum rate. The substrate (40) material can be silicon (Si) and the quantum dot (41) material can be germanium (Ge). The substrate (40) material can be Si or Ge and the quantum dot (41) material can be a rare earth. The substrate material (40) can be silicon oxide and the quantum dot (41) material can be silicon nitride.

公开(公告)号：FR2857155A1

公开(公告)日：2005-01-07

申请号：FR0307982

申请日：2003-07-01

Applicant: ST MICROELECTRONICS SA

Inventor： HALIMAOUI AOMAR ,  BENSAHEL DANIEL

IPC: H01L21/20 ,  H01L21/324 ,  H01L21/322

Abstract: Fabrication of a stressed layer of silicon or silicon-germanium alloy comprises: (a) formation of a layer (2) of silicon or silicon-germanium alloy on a layer (1) of a material having a modifiable mesh parameter; and (b) modification of the mesh parameter.

公开(公告)号：FR2853452A1

公开(公告)日：2004-10-08

申请号：FR0304008

申请日：2003-04-01

Applicant: ST MICROELECTRONICS SA

Inventor： COSNIER VINCENT ,  MORAND YVES ,  KERMARREC OLIVIER ,  BENSAHEL DANIEL ,  CAMPIDELLI YVES

IPC: H01L21/28 ,  H01L29/49 ,  H01L29/51

Abstract: The fabrication of a semiconductor device having a dielectric grid of a material with a high dielectric permittivity includes a stage (40) of deposition, directly on the grid dielectric, of a first layer of Si1-xGex with 0.5 less than x = 1, at a temperature essentially low with respect to the temperature of deposition of poly-Si by thermal chemical vapour deposition. An independent claim is also claimed for the semiconductor device thus fabricated.

公开(公告)号：FR2826177A1

公开(公告)日：2002-12-20

申请号：FR0107861

申请日：2001-06-15

Applicant: ST MICROELECTRONICS SA

Inventor： BENSAHEL DANIEL ,  HALIMAOUI AOMAR

IPC: H01L21/02 ,  H01L21/306 ,  H01L23/15 ,  H01L27/08 ,  H05K1/03

Abstract: An essentially plane silicon based substrate (1) comprises, in at least one zone (2) of the substrate, some grains (3) and some interstices (4) between the grains distributed over the whole thickness of the substrate at the level of this zone, in such a manner that the substrate presents a porosity of at least 20 % at all points of the volume of the substrate at the level of this zone. Independent claims are also included for: (a) a semiconductor or electronic product incorporating such a substrate; (b) a method for the fabrication of such a substrate; (c) a semiconductor or electronic product obtained by use of this method.

公开(公告)号：FR2812763B1

公开(公告)日：2002-11-01

申请号：FR0010346

申请日：2000-08-04

Applicant: ST MICROELECTRONICS SA

Inventor： BENSAHEL DANIEL ,  KERMARREC OLIVIER ,  CAMPIDELLI YVES

IPC: H01L21/20 ,  H01L29/12 ,  H01L33/00 ,  H01L33/06 ,  H01L21/205

Abstract: L'invention concerne un procédé de formation, sur un substrat semiconducteur monocristallin (40) d'un premier matériau, de boîtes quantiques (41) en un second matériau, consistant à faire croître par épitaxie en phase gazeuse le second matériau sur le premier matériau dans des conditions optimales propres à assurer une croissante à une vitesse contrôlable maximum. Dans une étape initiale, on envoie sur le substrat une bouffée d'un gaz comprenant le second matériau, dans des conditions correspondant à une vitesse de dépôt nettement plus rapide que ladite vitesse contrôlable maximum.