公开(公告)号：FR2824413A1

公开(公告)日：2002-11-08

申请号：FR0106091

申请日：2001-05-07

Applicant: ST MICROELECTRONICS SA

Inventor： DRAY CYRILLE ,  FOURNEL RICHARD ,  THOMAS SIGRID

IPC: G11C16/04 ,  G11C16/02

Abstract: The memory store is organized in words according to an array of rows and columns, and the selection of a word is ensured by the signals for selecting a row and a column (Selrow,Selcol), where the signals are delivered by two address decoders (DECX,DECYm). Each memory-cell word (M0,0) regroups several, in particular 8 for 8-bit word, memory cells (C0,...,C7) on the same row, and each cell comprises a memory transistor of MOS type with a control gate and two channel electrodes the drainn and the source; the control gates of the cells of each row are connected together to a gate control line (CG0), and the drain of each cell is connected to the respective bit line (B10,...,B17). Each word comprises a word-selecting transistor (TS0,0) by the source, and is controlled by the low-voltage selection signals (SelRow,SelCol). The gate control lines (CG0,...Cgm-1) are controlled by a polarization circuit (1) receiving the address selection signals. The gate control lines are regrouped at least two by two, and each group is controlled by a higher-voltage switching circuit of the polarization circuit. The gate control lines put together correspond to the to the neighbouring rows. The higher-voltage switching circuit applies either the higher voltage (Vpp) in the case of the write instruction, or a stationary voltage (Vrepos) applied outside of the write operation. The level of stationary voltage is chosen as equal to the level of polarization voltage in the read mode. Each column of memory store comprises bit lines (B10,...,B17), connected to a write circuit (2) for writing (DATA-IN) and to a read circuit (3) for reading (DATA-OUT). The read circuit (3) comprises a precharge circuit associated with a detection circuit comprising differential amplfiers, and the precharge circuit receives an activation instruction before the start of a cycle or a succession of cycles of the read operations. The precharge circuit brings all bit lines to the same precharge voltage (Vpch). The memory store comprises an isolating circuit (EI) between the bit lines and the read circuit (3), which is activated during the write operations. An integrated circuit comprises the read-only memory store of specified architecture.

公开(公告)号：FR2823900A1

公开(公告)日：2002-10-25

申请号：FR0105343

申请日：2001-04-20

Applicant: ST MICROELECTRONICS SA

Inventor： DRAY CYRILLE ,  FOURNEL RICHARD

IPC: G11C16/04 ,  H01L27/115 ,  H01L29/66

Abstract: The memory store comprises one or more cells (C1,C2,C3) where each cell contains a transistor of type FAMOS (T1) whose gate is insulated, and two access transistors (T2,T3) whose respective gates, sources and drains are connected together. The drains of the access transistors (T2,T3) are connected to the source of the insulated-gate transistor (T1). An isolating transistor (T4) is connected between two neighbouring cells (C1,C2) so that the drain and the source are connected to the sources of the insulated-gate transistors of the neighbouring cells of the same word line (WL). The drain of the insulated-gate transistor (T1) is connected to the associated bit line (BL1). The gates of the access transistors (T2,T3) are connected to the word line (WL), and the sources are connected to a supply line (SL). The insulating transistor (T4) and the access transistors (T2,T3) of all cells have a common gate. The insulated-gate transistor (T1) and the access transistors (T2,T3) of the first or the second cell on one hand, and the isolating transistor (T4) on the other hand, are implemented in the same well. The insulated-gate transistor has a ring structure which comprises a central diffusion zone, a peripheral diffusion zone, and an intermediate polysilicon zone. The structure also comprises a separation zone which includes a bar substantially perpendicular to an axis passing through the centres of the cells, and barriers substantially parallel to the axis. A memory store comprises M x N insulated-gate transistors having ring structure which are laid-out in N rows and M columns, where the central diffusion zone forms the drain and the peripheral diffusion zone forms the source of the insulated-gate transistors; for each row the separation zone separates M insulated-gate transistors and comprises two barriers substantially parallel to the axis of the insulated-gate transistors, and M-1 bars perpendicular to the barriers. The separation zones of rows of ranks n and n+1 where n is an integer from N to N-1, have a contact line in common situated between the two barriers.

公开(公告)号：FR2911450A1

公开(公告)日：2008-07-18

申请号：FR0700267

申请日：2007-01-15

Applicant: ST MICROELECTRONICS SA

Inventor： BARASINSKI SEBASTIEN ,  DRAY CYRILLE

IPC: H03K19/0185 ,  H03K5/12

Abstract: L'invention concerne un circuit tampon susceptible de transférer entre une entrée (IN) et une sortie (OUT) un signal d'entrée comprenant au moins un front montant et/ou un front descendant,ledit circuit comprenant un premier inverseur CMOS (10), dont l'entrée est reliée à l'entrée (IN) du circuit, et dont la sortie est montée en série avec l'entrée d'un deuxième inverseur CMOS (20), la sortie dudit deuxième inverseur CMOS (20) étant reliée à la sortie (OUT) du circuit.Le circuit est essentiellement caractérisé en ce qu'il comprend en outre des moyens pour créer une surtension sur les deux inverseurs CMOS (10, 20).En particulier, les moyens pour créer une surtension comprennent des moyens de stockage d'énergie électrique (C1, C2) et des moyens de contrôle (30, 40, TRI1, TRI2) pour libérer sélectivement l'énergie stockée par les moyens de stockage (C1, C2).

公开(公告)号：FR2895136A1

公开(公告)日：2007-06-22

申请号：FR0512871

申请日：2005-12-19

Applicant: ST MICROELECTRONICS SA

Inventor： DRAY CYRILLE ,  GAMET STEPHANE

IPC: G11C16/14

Abstract: L'invention concerne un dispositif de commutation d'ordre n, comprenant :&circlef; une première branche comprenant n transistors associés en série entre une première entrée (E1) sur laquelle est appliqué un potentiel (V0,n) de rang 0 et une sortie,&circlef; une deuxième branche comprenant n transistors associés en série une deuxième entrée (E2) sur laquelle est appliqué un potentiel (Vn,o) de rang n et la sortie,Le dispositif selon l'invention comprend également :&circlef; un moyen pour produire n-1 potentiels de rang 1 à n-1 compris entre le potentiel de rang 0 et le potentiel de rang n,&circlef; un moyen de pilotage pour, à partir des n+1 potentiels de rang 0 à n, produire des signaux de commande appropriés pour piloter les grilles des transistors de la première branche et de la deuxième branche de sorte que les transistors de l'une des branches soient passants et les transistors de l'autre des branches soient bloqués, en fonction de la valeur du potentiel de rang n par rapport à la valeur du potentiel de rang 0.

公开(公告)号：FR2871921A1

公开(公告)日：2005-12-23

申请号：FR0406532

申请日：2004-06-16

Applicant: ST MICROELECTRONICS SA

Inventor： DRAY CYRILLE ,  BARASINSKI SEBASTIEN ,  LASSEUGUETTE JEAN ,  FREY CHRISTOPHE ,  FOURNEL RICHARD

IPC: G11C7/18 ,  G11C8/10 ,  G11C11/16

Abstract: L'invention concerne un dispositif de mémoire, comprenant au moins une ligne d'écriture segmentée (10) formée d'au moins un segment d'écriture, dotée de moyens de programmation (90), lesdits moyens de programmation (90) étant commandés par des moyens d'adressage de ligne (190) en mode écriture dudit dispositif de mémoire, pour programmer au moins une cellule mémoire (30) couplée à ladite ligne d'écriture segmentée, une ligne de bit de lecture (150) étant reliée à un circuit de lecture (110) pour lire le contenu de ladite cellule en mode lecture dudit dispositif de mémoire, caractérisé en ce que ladite ligne de bit de lecture coopère en mode écriture avec lesdits moyens d'adressage de ligne pour commander lesdits moyens de programmation de ladite ligne d'écriture segmentée.

公开(公告)号：FR2829279B1

公开(公告)日：2003-12-12

申请号：FR0111381

申请日：2001-09-03

Applicant: ST MICROELECTRONICS SA

Inventor： DRAY CYRILLE ,  CASPAR DANIEL ,  FOURNEL RICHARD

IPC: G11C16/02 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  G11C16/04

公开(公告)号：FR2824413B1

公开(公告)日：2003-07-25

申请号：FR0106091

申请日：2001-05-07

Applicant: ST MICROELECTRONICS SA

Inventor： DRAY CYRILLE ,  FOURNEL RICHARD ,  THOMAS SIGRID

IPC: G11C16/04 ,  G11C16/02

Abstract: A non-volatile memory architecture with a word-based organization includes one selection transistor per word. This selection transistor is used for the selection of the word by the source of the memory cells. In this way, the selection may be done directly by the ouput signals from the address decoders using low voltage. The switching of a high voltage to the gates and the drains of the memory cells is done independently of this selection. This enables the required number of high voltage switches to be reduced.

公开(公告)号：FR2888660A1

公开(公告)日：2007-01-19

申请号：FR0507548

申请日：2005-07-13

Applicant: ST MICROELECTRONICS SA

Inventor： DRAY CYRILLE

IPC: G11C7/14 ,  G11C11/14

Abstract: L'invention concerne un système de redondance pour une mémoire (10) organisée en une pluralité de sous-espaces mémoire (db ) comprenant chacun leur circuit de lecture (SA ), des moyens de redondance colonne (Blred) étant prévus au sein de chaque sous-espace pour suppléer à au moins une colonne défectueuse dudit sous-espace, ledit système comprenant un contrôleur de mémoire (20) prévu pour interagir avec ladite mémoire par l'intermédiaire d'un bus d'écriture (TD) et d'un bus de lecture (Q), ledit système étant caractérisé en ce que le contrôleur de mémoire comprend des moyens de génération d'un signal (TD ) d'activation des moyens de redondance colonne, ledit signal étant prévu pour être convoyé à destination des circuits de lecture (SA ) de la mémoire auxquels est connecté le bus d'écriture (TD), de manière à activer, par l'intermédiaire desdits circuits de lecture, les moyens de redondance colonne des sous-espaces mémoire comprenant une adresse de colonne défectueuse.

公开(公告)号：FR2859327B1

公开(公告)日：2005-11-25

申请号：FR0310322

申请日：2003-08-29

Applicant: ST MICROELECTRONICS SA

Inventor： DRAY CYRILLE

IPC: G11C16/12 ,  H03K17/16 ,  G11C5/14

Abstract: The switching circuit comprises three circuits allowing the connection between the node and one of three other nodes which provide the three voltages. Control ensures a mutually exclusive switching mode preventing any crossover current. The switching circuit is provided to switch a node to one of three possible supply voltages (GND, V33, V55) as a function of two control signals (ERASE, PROG). The device comprises three circuits allowing the connection between the node and one of three other nodes which provide the three voltages. The device is controlled by control signals CDENMOS, CDEPMOS, Z1 & Z2, READPATH & PROGPATH, which together ensure a mutually exclusive switching mode and preventing any crossover current. The device uses MOS transistors with a low nominal voltage, which is lower than that of the highest switched voltage.

公开(公告)号：FR2838554B1

公开(公告)日：2004-07-09

申请号：FR0209454

申请日：2002-07-25

Applicant: ST MICROELECTRONICS SA

Inventor： FOURNEL RICHARD ,  DRAY CYRILLE ,  GENDRIER PHILIPPE

IPC: H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/02

Abstract: The semiconductor memory device comprises a transistor with floating gate (FG) and a control gate, where the regions of source (S), drain (D) and channel of the floating-gate transistor form the control gate, and the memory cell comprises a dielectric zone (ZTN) laid out between a part (P1) of the layer of gate material and an active semiconductor zone (RG1) electrically insulated from another active zone (RG2) incorporating the control gate. The dielectric zone forms a tunnel zone (ZTN) for transferring the charges stored in the floating gate at the time of erasing the memory cell. The capacitive value of tunnel zone (ZTN) is below or equal to 30% of the total capacitive value between the layer of gate material and the set of active zones of the memory cell. The transistor has a ring gate (FG), and the gate material comprises a linking part (PL) connecting the first part (P1) and the ring gate. The active zones (RG1,RG2) are electrically insulated by the p-n junctions polarized in reverse, and the two zones are electrically insulated on the surface by a region of shallow trench isolation (STI). A memory array comprises several memory cells, each memory cell is associated with an access transistor, and the access transistor partly surrounds the floating-gate transistor of the memory cell resulting in a memory array of reduced size and lower programming currents. The device comprises the polarization means possessing the states of programming, reading and erasing the memory cell, where the erasing is of type Fowler-Nordheim and applies a voltage on the first active zone which is much higher than that applied in the regions of source, drain and substrate of the transistor. The programming of type Fowler-Nordheim applies to the regions of source, drain and substrate of the transistor voltages which are much higher than those applied to the first active zone. In the reading state the difference between the drain/source voltages is limited to 1 V in absolute value. An integrated circuit comprises the device as claimed.