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    Semiconductor device for electrically erasable and programmable read-only memory (EEPROM) with only one layer of gate material, and corresponding memory array
    14.
    发明专利
    Semiconductor device for electrically erasable and programmable read-only memory (EEPROM) with only one layer of gate material, and corresponding memory array 未知

    公开(公告)号：FR2838554A1

    公开(公告)日：2003-10-17

    申请号：FR0209454

    申请日：2002-07-25

    Applicant: ST MICROELECTRONICS SA

    Inventor： FOURNEL RICHARD ,  DRAY CYRILLE ,  GENDRIER PHILIPPE

    IPC: H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/02

    Abstract: The semiconductor memory device comprises a transistor with floating gate (FG) and a control gate, where the regions of source (S), drain (D) and channel of the floating-gate transistor form the control gate, and the memory cell comprises a dielectric zone (ZTN) laid out between a part (P1) of the layer of gate material and an active semiconductor zone (RG1) electrically insulated from another active zone (RG2) incorporating the control gate. The dielectric zone forms a tunnel zone (ZTN) for transferring the charges stored in the floating gate at the time of erasing the memory cell. The capacitive value of tunnel zone (ZTN) is below or equal to 30% of the total capacitive value between the layer of gate material and the set of active zones of the memory cell. The transistor has a ring gate (FG), and the gate material comprises a linking part (PL) connecting the first part (P1) and the ring gate. The active zones (RG1,RG2) are electrically insulated by the p-n junctions polarized in reverse, and the two zones are electrically insulated on the surface by a region of shallow trench isolation (STI). A memory array comprises several memory cells, each memory cell is associated with an access transistor, and the access transistor partly surrounds the floating-gate transistor of the memory cell resulting in a memory array of reduced size and lower programming currents. The device comprises the polarization means possessing the states of programming, reading and erasing the memory cell, where the erasing is of type Fowler-Nordheim and applies a voltage on the first active zone which is much higher than that applied in the regions of source, drain and substrate of the transistor. The programming of type Fowler-Nordheim applies to the regions of source, drain and substrate of the transistor voltages which are much higher than those applied to the first active zone. In the reading state the difference between the drain/source voltages is limited to 1 V in absolute value. An integrated circuit comprises the device as claimed.

    Method for erasing memory cell of type FAMOS and corresponding memory-cell device, by electrical means
    17.
    发明专利
    Method for erasing memory cell of type FAMOS and corresponding memory-cell device, by electrical means 未知

    公开(公告)号：FR2823363A1

    公开(公告)日：2002-10-11

    申请号：FR0104621

    申请日：2001-04-05

    Applicant: ST MICROELECTRONICS SA

    Inventor： FOURNEL RICHARD ,  DRAY CYRILLE ,  CASPAR DANIEL

    IPC: G11C16/02 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/14

    Abstract: The method is for electrical erasing of a memory cell (CM) of type FAMOS, which comprises a p-MOS transistor with a floating gate which is not connected. The erasing is by the application of determined voltages to the bulk (B), the source (S) and the drain (D) of the transistor by an erasing module (MEF), that is a voltage VB to the bulk, which is higher than at last 4-6 V, with still lower voltages VS and VD applied to the source and the drain, respectively, and below a limiting voltage which causes the destruction of the cell, which is about 10 V. The difference between voltages applied to the source and the drain is non-null and positive, and below a predetermined threshold, which is about 1 V. For example, in the case of 0.18 micrometer technology, the source voltage is about 1 V, the drain voltage null, and the bulk voltage about 7-8 V, and the erasing takes about 1 minute. The difference between the source and the drain voltages is variable in the course of erasing process. The memory device comprises an electrically erasable memory cell (CM) of type FAMOS. The p-MOS transistor of the memory cell has a standard linear configuration, or more advantageously a ring ocnfiguration which comprises a central electrode surrounded by the gate and a peripheral electrode. The device comprises programming means for writing data into the memory cell, reading means for reading the content of the memory cell, and control means for selectively connecting the means for programming, reading and erasing of the memory cell. The device comprises several electrically erasable memory cells of type FAMOS. The memory device is a part of an integrated circuit.

    18.
    发明专利
    未知

    公开(公告)号：FR2820545A1

    公开(公告)日：2002-08-09

    申请号：FR0101442

    申请日：2001-02-02

    Applicant: ST MICROELECTRONICS SA

    Inventor： FOURNEL RICHARD ,  SEDJAI LEILA

    IPC: G11C16/34 ,  G11C29/34 ,  H01L21/8247

    Abstract: The invention relates to a method for the simultaneous verification of a first electrical state of a group of N cells from a non-volatile memory. The inventive method is characterised in that it comprises the following steps: the N memory cells (CE) to be verified and the verification cell (Cveri) are read and selected simultaneously; the N signals which are read are added together to produce a sum signal; the sum signal is compared to the signal which is read on the verification cell (Cveri) in order to provide a certain state signal when the sum signal is less than the signal which is read on the verification cell (Cveri), indicating that the N memory cells are in said electrical state, and another electrical state signal when the sum signal is greater than the signal which is read on the verification cell, indicating that at least one memory cell is not in said electrical state.

    20.
    发明专利
    未知

    公开(公告)号：FR2801719B1

    公开(公告)日：2002-03-01

    申请号：FR9915114

    申请日：1999-11-30

    Applicant: ST MICROELECTRONICS SA

    Inventor： FOURNEL RICHARD ,  VARISCO LAURA

    IPC: G11C7/08 ,  G11C7/12 ,  G11C16/24 ,  G11C16/28

    Abstract: A device for reading a memory including precharging circuits for precharging the inputs of a differential amplifier to a precharging voltage. The precharging voltage may be at an intermediate voltage level between a precharging voltage level of the bit lines and the voltage level of the logic supply voltage. This provides for a very fast build-up, during a following evaluation phase, of the output of the amplifier in a state corresponding to that of the cell being read. An internal detection circuit may also be included to detect an end of the precharging to stop the precharging circuit and activate the read current generator for the evaluation phase.

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