公开(公告)号：DE602004000562D1

公开(公告)日：2006-05-18

申请号：DE602004000562

申请日：2004-07-09

Applicant: ST MICROELECTRONICS SA

Inventor： TEGLIA YANNICK ,  LIARDET PIERRE-YVAN

IPC: G06F11/00 ,  G06F1/00 ,  G06F11/07 ,  G06F21/52 ,  G06F21/71

Abstract: A non-volatile memory (22) stores value of the verification of an invariant, and periodically recalculates the value in volatile memory. A circuit (21) holds an invariant in normal operation of the processor (1), and compares with stored invariant to detect loss of invariant and occurrence of disturbance in processor. An independent claim is also included for integrated processor.

公开(公告)号：DE60023770D1

公开(公告)日：2005-12-15

申请号：DE60023770

申请日：2000-02-18

Applicant: ST MICROELECTRONICS SA

Inventor： LIARDET PIERRE-YVAN ,  ROMAIN FABRICE ,  PLESSIER BERNARD ,  HENNEBOIS BRIGITTE

IPC: H04L9/06 ,  H04L9/08 ,  H04L9/30

Abstract: The secure coprocessor encryption technique has a memory module (30) and a battery of input/output registers (32). A multiplexer (34) transfers the digital words between the input/output register and the input register (36). There is a key register (38) and processing module (42). The battery of input/output registers has an external noise interference register (50) showing when the encryption/de encryption and digital key are at risk.

公开(公告)号：DE602006020010D1

公开(公告)日：2011-03-24

申请号：DE602006020010

申请日：2006-12-18

Applicant: ST MICROELECTRONICS SA

Inventor： TEGLIA YANNICK ,  LIARDET PIERRE-YVAN ,  POMET ALAIN

IPC: H04L9/06

公开(公告)号：DE602005009439D1

公开(公告)日：2008-10-16

申请号：DE602005009439

申请日：2005-07-05

Applicant: PROTON WORLD INT NV ,  ST MICROELECTRONICS SA

Inventor： DAEMEN JOAN ,  GUILLEMIN PIERRE ,  ANGUILLE CLAUDE ,  BAEDOUILLET MICHEL ,  LIARDET PIERRE-YVAN ,  TEGLIA YANNICK

IPC: H04L9/18 ,  G06F12/14 ,  G06F21/00

Abstract: The method involves applying a ciphering algorithm with a function of a key specific to an integrated circuit of an initialization vector. A ciphered data is memorized, where the initialization vector includes a storage address of the data in a memory and a differentiation value. An algorithm identical to the ciphering algorithm is applied based on the address of the ciphered data. An independent claim is also included for a smart card comprising an electronic assembly.

公开(公告)号：DE602004015374D1

公开(公告)日：2008-09-11

申请号：DE602004015374

申请日：2004-07-30

Applicant: ST MICROELECTRONICS SA

Inventor： TEGLIA YANNICK ,  LIARDET PIERRE-YVAN

IPC: G06F21/24 ,  G06F21/22 ,  H04L9/06 ,  H04L9/10

Abstract: The functional processes are divided into steps such that each process is interrupted with the storage of intermediary result, at the end. The steps of consecutive processes are executed successively and the process of next step is selected according to the result of random drawing of a number. An independent claim is also included for processor for executing identical functional processes.

公开(公告)号：DE60004409T2

公开(公告)日：2004-06-09

申请号：DE60004409

申请日：2000-01-18

Applicant: ST MICROELECTRONICS SA

Inventor： LIARDET PIERRE-YVAN

IPC: G06F7/58 ,  H03K3/84

Abstract: The random number generator circuit receives digital input signals (Se) from a noise source (1). A pseudo random number generator (3) is passed a digital signal (Si) from the logic circuit. A memory unit (5) collects the random generator output (Ss) and passes a signal back to the logic circuit (Sr). The resultant output signal from the random generator is passed to the output interface (4).

公开(公告)号：DE602007012805D1

公开(公告)日：2011-04-14

申请号：DE602007012805

申请日：2007-08-29

Applicant: ST MICROELECTRONICS SA

Inventor： LIARDET PIERRE-YVAN ,  TEGLIA YANNICK

IPC: G06F7/72

公开(公告)号：DE602004029536D1

公开(公告)日：2010-11-25

申请号：DE602004029536

申请日：2004-08-27

Applicant: ST MICROELECTRONICS SA

Inventor： LIARDET PIERRE-YVAN ,  TEGLIA YANNICK ,  TOMEI AMBROISE

IPC: G06F7/58 ,  G06F9/30

公开(公告)号：DE602005022039D1

公开(公告)日：2010-08-12

申请号：DE602005022039

申请日：2005-12-13

Applicant: ST MICROELECTRONICS SA

Inventor： LIARDET PIERRE-YVAN ,  TEGLIA YANNICK

IPC: H04L9/06

公开(公告)号：DE602005017550D1

公开(公告)日：2009-12-24

申请号：DE602005017550

申请日：2005-09-14

Applicant: ST MICROELECTRONICS SA

Inventor： LIARDET PIERRE-YVAN ,  TEGLIA YANNICK

IPC: H04L9/06

Abstract: The method involves executing an algorithm with a valid data between several executions of same algorithm with an invalid data corresponding to a combination of the valid data with predetermined masks. The masks are selected so that result of application of the algorithm with same key is different for one bit from result of application of the algorithm to the valid data. An independent claim is also included for a processor for executing an encryption algorithm.