公开(公告)号：DE60216646T2

公开(公告)日：2007-10-11

申请号：DE60216646

申请日：2002-01-09

Applicant: ST MICROELECTRONICS SA

Inventor： MENUT OLIVIER ,  GRIS YVON

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/20 ,  H01L21/205 ,  H01L21/329 ,  H01L21/822 ,  H01L27/04 ,  H01L29/861

Abstract: Semiconductor single crystal substrate is made by forming an initial single crystal substrate (1) having lattice discontinuity locally on its surface, amorphizing the lattice around periphery of a recess formed at the discontinuity, depositing amorphous material the same as that of initial substrate on the obtained structure, and thermally annealing, to recrystallize the amorphous material. Production of a semiconductor single crystal substrate involves: (a) Forming an initial single crystal substrate (1), then successively depositing on the initial substrate (1) a first layer (2) of a first material and a second layer (3) of a second material, and etching a trench (4) which is subsequently filled with a filling material and which forms a lattice discontinuity in the single crystal lattice; (b) Performing selective etching with respect to the second layer (3), the first layer (2) and an upper part of the filling material of the trench (4), so as to form lateral cavities and a recess at the level of the single crystal discontinuity, and removing the second layer (3); (c) Amorphizing the single crystal lattice around the periphery of the recess; (d) Depositing a layer of amorphous material having the same chemical composition as that of the initial substrate (1) on the obtained structure; and (e) Thermally annealing the structure, in order to recrystallize the amorphous material so that it becomes continuous with the single crystal lattice of the initial substrate. The initial substrate is selected from silicon, germanium, silicon carbide, gallium arsenide, and an alloy containing at least some of these materials. The amorphization stage (c) involves localized ion implantation around the recess by using a mask. Amorphization is self-aligned on the trench (4). Either before or after stage (e), the surface of the structure is planarized, preferably by chemical-mechanical polishing. An Independent claim is given for an integrated circuit comprising a single crystal silicon substrate produced by the above process, and comprising at least two adjacent transistors produced in the body of the substrate that includes at least one buried trench forming an isolating trench separating the buried layers adjacent to the transistors.

公开(公告)号：FR2826178B1

公开(公告)日：2004-11-05

申请号：FR0107717

申请日：2001-06-13

Applicant: ST MICROELECTRONICS SA

Inventor： MENUT OLIVIER ,  JAOUEN HERVE

IPC: H01L21/331 ,  H01L21/477 ,  H01L27/04

Abstract: A method of fabricating an integrated circuit including a monocrystalline silicon substrate, a layer of polycrystalline silicon on the top surface of the substrate and doped with at least two dopants with different rates of diffusion, in which method annealing is performed at a temperature and for a time such that a first dopant diffuses into a first zone and a second dopant diffuses into a second zone larger than the first zone.

公开(公告)号：FR2819630B1

公开(公告)日：2003-08-15

申请号：FR0100416

申请日：2001-01-12

Applicant: ST MICROELECTRONICS SA

Inventor： MENUT OLIVIER ,  BOUCHE GUILLAUME ,  JAOUEN HERVE

IPC: H01L21/762 ,  H01L21/76 ,  H01L27/118

公开(公告)号：FR2823598A1

公开(公告)日：2002-10-18

申请号：FR0105015

申请日：2001-04-12

Applicant: ST MICROELECTRONICS SA

Inventor： MENUT OLIVIER ,  JAOUEN HERVE ,  ROBILLIART ETIENNE

IPC: H01L21/336 ,  H01L29/417 ,  H01L29/78

Abstract: The production of an MOS transistor involves the realization of a MOS transistor of which the gate length, and by consequence essentially the channel length (CHL), is less than the technological limits of photolithography, by forming internal spacers (13) in a cavity of an insulating layer (8) prior to the deposition of the gate material (15). Moreover, the drain and source layers (7) are insulated from the substrate by buried insulating layers (6). Independent claims are also included for the following: (a) a MOS transistor produced as above; and (b) an integrated circuit incorporating at least one MOS transistor thus obtained.

公开(公告)号：FR2819630A1

公开(公告)日：2002-07-19

申请号：FR0100416

申请日：2001-01-12

Applicant: ST MICROELECTRONICS SA

Inventor： MENUT OLIVIER ,  BOUCHE GUILLAUME ,  JAOUEN HERVE

IPC: H01L21/762 ,  H01L21/76 ,  H01L27/118

Abstract: A semiconductor device comprises a semiconductor substrate (SB) incorporating locally at least one zone (ZL) emerging at the surface and entirely edged, at its lateral edges and it bottom, by an insulating material rendering it entirely insulated from the rest of the substrate. The horizontal insulating layer may be with a constant thickness or crenellated. An Independent claim is also included for a method for the fabrication of this semiconductor device.

公开(公告)号：FR3006095A1

公开(公告)日：2014-11-28

申请号：FR1354713

申请日：2013-05-24

Applicant: ST MICROELECTRONICS SA

Inventor： MENUT OLIVIER ,  TURGIS DAVID ,  CIAMPOLINI LORENZO

IPC: G11C15/04 ,  G11C11/401

Abstract: Cellule (1) de mémoire adressable par contenu ternaire, configurée pour comparer une donnée binaire d'entrée présente au niveau d'une borne d'entrée SL de la cellule, avec deux données binaires de référence, et délivrer un signal de concordance au niveau d'une ligne de concordance ML à laquelle est reliée ladite cellule, ladite cellule incluant : • un premier circuit de stockage(2) dont un point (23) est à un potentiel représentatif de la première donnée binaire de référence ; • un second circuit de stockage (3) dont un point (33) est à un potentiel représentatif de la seconde donnée binaire de référence ; • un circuit de comparaison (4), connecté auxdits points (23, 33) des premier et second circuits de stockage (23), et à ladite borne d'entrée SL de la cellule, et présentant un point de comparaison (50) dont le potentiel est représentatif de la comparaison de la donnée binaire d'entrée avec les première et seconde données de référence, dans lequel ledit point de comparaison (50) est connecté à un étage de sortie (5), ledit étage de sortie étant connecté à la ligne de concordance ML, et configuré pour délivrer sur la ligne de concordance un signal fondé sur le potentiel du point de comparaison.

公开(公告)号：AT557420T

公开(公告)日：2012-05-15

申请号：AT11152553

申请日：2011-01-28

Applicant: ST MICROELECTRONICS SA ,  ST MICROELECTRONICS CROLLES 2 ,  COMMISSARIAT ENERGIE ATOMIQUE

Inventor： MENUT OLIVIER ,  BERGHER LAURENT ,  YESILADA EMEK ,  TROUILLER YORICK ,  FOUSSADIER FRANCK ,  BINGERT RAPHAEL

IPC: H01L27/02 ,  G06F17/50 ,  H01L21/8234 ,  H01L27/085 ,  H01L27/118

Abstract: The library has cell with a minimum dimension metal oxide semiconductor transistor and a cell (41) with a low leakage current metal oxide semiconductor transistor, where the two cells occupy a same surface. The low leakage current metal oxide semiconductor transistor has a gate (47) whose length (Lmin) is same as that of the gate of the minimum dimension metal oxide semiconductor transistor over a width (W1) in a central part. Another length (L2) of the low leakage current metal oxide semiconductor transistor is greater than another width (W2) of both sides of the central part. An independent claim is also included for a method for synthesis of a part of an integrated circuit from the cell library.

公开(公告)号：FR2956247A1

公开(公告)日：2011-08-12

申请号：FR1050891

申请日：2010-02-09

Applicant: ST MICROELECTRONICS SA ,  ST MICROELECTRONICS CROLLES 2 ,  COMMISSARIAT ENERGIE ATOMIQUE

Inventor： MENUT OLIVIER ,  BERGHER LAURENT ,  YESILADA EMEK ,  TROUILLER YORICK ,  FOUSSADIER FRANCK ,  BINGERT RAPHAEL

IPC: H01L27/085

Abstract: L'invention concerne une bibliothèque de cellules destinée à être utilisée pour réaliser un circuit intégré, cette bibliothèque définissant une première cellule comprenant un premier transistor MOS de dimensions minimales, et une deuxième cellule (41) comprenant un deuxième transistor MOS à plus faible courant de fuite, dans laquelle la deuxième cellule occupe la même surface que la première cellule, et le deuxième transistor MOS a une grille (47) de même longueur (Lmin) que la grille du premier transistor MOS sur au moins une première largeur (W1) dans sa partie centrale, et de longueur (L2) supérieure sur au moins une seconde largeur (W2) de part et d'autre de la partie centrale.

公开(公告)号：FR2819636B1

公开(公告)日：2003-09-26

申请号：FR0100418

申请日：2001-01-12

Applicant: ST MICROELECTRONICS SA

Inventor： MENUT OLIVIER ,  GRIS YVON

IPC: H01L21/20 ,  H01L21/8242 ,  H01L27/108 ,  H01L27/07

Abstract: DRAM memory cell is made by forming an initial single crystal substrate having a trench capacitor that forms a crystal lattice discontinuity, amorphizing the lattice around periphery of a recess formed at the discontinuity, depositing amorphous material the same as that of initial substrate on obtained structure, thermally annealing, and forming an access transistor in contact with the trench. Fabrication of an integrated circuit comprising a semiconductor substrate (SB) supporting a DRAM memory cell comprising an access transistor (T) and a storage capacitor (TRC) comprises: (a) Producing an initial substrate having a local trench capacitor containing a polycrystalline filling material that emerges from the surface of the initial substrate and forms a discontinuity of the crystal lattice; (b) Forming a recess in the initial substrate at the level of the trench; (c) Amorphizing, locally and self-aligned on the trench, the single crystal lattice of the substrate at the periphery of the recess and the part of the filling material that emerges from the trench; (d) Depositing on the obtained structure a layer of amorphous material having the same chemical composition as that of the initial substrate; (e) Thermally annealing the obtained structure, in order to recrystallize the amorphous material so that it becomes continuous with the single crystal lattice of the initial substrate; and (f) Epitaxially growing an upper layer of the substrate, in and on which is produced an access transistor (T) whose source (S) or drain (D) region contacts the trench capacitor forming the storage capacitor (TRC) of the DRAM memory cell. The initial substrate production stage (a) involves successively depositing on the initial substrate a first layer of a first material and a second layer of a second material, and etching a trench, which is subsequently filled with a filling material. The recess forming stage (b) involves performing selective etching with respect to the second layer, the first layer and an upper part of the filling material of the trench, so as to form lateral cavities and a recess at the level of the single crystal discontinuity, and removing the second layer. The amorphization stage (c) involves localized ion implantation around the recess by using a mask. Either before or after stage (e), the surface of the structure is planarized, preferably by chemical-mechanical polishing. An Independent claim is given for an integrated circuit fabricated by the above process and supporting a DRAM memory cell comprising a transistor (T) and a storage capacitor (TRC).

公开(公告)号：FR2819637B1

公开(公告)日：2003-05-30

申请号：FR0100420

申请日：2001-01-12

Applicant: ST MICROELECTRONICS SA

Inventor： MENUT OLIVIER ,  GRIS YVON

IPC: H01L27/144 ,  H01L27/146 ,  H01L31/0352 ,  H01L31/103 ,  H01L31/18

Abstract: An integrated circuit is provided that includes a substrate incorporating a semiconductor photodiode device having a p-n junction. The photodiode device includes at least one capacitive trench buried in the substrate and connected in parallel with the junction. In a preferred embodiment, the substrate is formed from silicon, and the capacitive trench includes an internal doped silicon region partially enveloped by an insulating wall that laterally separates the internal region from the substrate. Also provided is a method for fabricating an integrated circuit including a substrate that incorporates a semiconductor photodiode device having a p-n junction.