公开(公告)号：DE69626631D1

公开(公告)日：2003-04-17

申请号：DE69626631

申请日：1996-06-05

Applicant: ST MICROELECTRONICS SRL

Inventor： CALLIGARO CRISTIANO ,  GASTALDI ROBERTO ,  MANSTRETTA ALESSANDRO ,  CAPPELLETTI PAOLO ,  TORELLI GUIDO

IPC: G11C16/02 ,  G11C11/56

公开(公告)号：DE69423104T2

公开(公告)日：2000-07-20

申请号：DE69423104

申请日：1994-10-31

Applicant: ST MICROELECTRONICS SRL

Inventor： CAPPELLETTI PAOLO

IPC: G06F12/16 ,  G06F11/10 ,  G11C7/00 ,  G11C11/56 ,  G11C29/42 ,  G06F11/00

Abstract: The invention relates to a multi-level storage device comprising: at least a first plurality (CP) of cells (C-0...C-N), each adapted for storing an identical first number (greater than one) of binary data (B0...B7), and at least a corresponding second plurality (WP) of cells adapted for storing a second number of error check and correcting words (W-0...W-7) equal to said first number, said words (W-0...W-7) being respectively associated with sets of binary data, each comprising at least one binary data for each cell in said first plurality (CP). In this way, many of the known error correction algorithms can be applied to obtain comparable results to those provided by binary memories. In addition, where multi-level cells are used for storing the error check and correcting words, the device dimension requirements can also be comparable.

公开(公告)号：DE69732637D1

公开(公告)日：2005-04-07

申请号：DE69732637

申请日：1997-12-22

Applicant: ST MICROELECTRONICS SRL

Inventor： CAPPELLETTI PAOLO ,  MAURELLI ALFONSO ,  OLIVO MARCO

IPC: G06F11/10 ,  G11C29/00 ,  G11C16/06 ,  G11C29/06 ,  G11C29/52

Abstract: A method of self-test and correction of errors due to a loss charge for a flash memory constituted by an array or matrix of cells (bits), organized in rows and columns, erasable and programmable by whole sectors in which the matrix is divided, implemented by realizing at least an additional row and at least an additional column of cells for each memory sector; storing parity codes is the additional row and column, and carrying out periodically a self-test routine and eventual correction routine composed of the following steps: repeating the sequential reading per bytes and parity check; verifying the consistency of the parity value with the value stored in the respective parity bit; if the verification is negative, retaining the current row address and proceeding to sequentially verify column parity starting from the first column until identifying the column for which the verification yields a negative result, and if the failed bit so individuated is "1" reprogramming it to "0".

公开(公告)号：DE69429264T2

公开(公告)日：2002-06-13

申请号：DE69429264

申请日：1994-09-27

Applicant: ST MICROELECTRONICS SRL

Inventor： CAPPELLETTI PAOLO ,  CASAGRANDE GIULIO

IPC: G11C17/00 ,  G11C16/04 ,  G11C16/16 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/00 ,  G11C16/06

Abstract: A byte erasable memory with an EEPROM type functionality that can be integrated in a fully compatible way with a standard FLAS-EPROM process is composed by a matrix of FLASH-EPROM cells organized in an n number of bytes each of an m number of bits addressable through a plurality of wordlines and bitlines. The EEPROM-type memory has an auxiliary selection structure composed of an n number of byte select transistors, a plurality of individually selectable source biasing lines and a plurality of select lines in the same number of the wordlines and selectable in a biunivocal way with the wordlines. The cells of a byte have a common source that is accessed and individually selectable through the respective select transistors. EEPROM functionality is obtained without any modification of the standard FLASH-EPROM fabrication process by splitting the voltage applied between a control gate and the respective common source region of the cells that compose a certain selected byte about a common ground potential, during a byte erasing phase thus reducing the electrical stress induced on deselected cells.

公开(公告)号：DE69423104D1

公开(公告)日：2000-03-30

申请号：DE69423104

申请日：1994-10-31

Applicant: ST MICROELECTRONICS SRL

Inventor： CAPPELLETTI PAOLO

IPC: G06F12/16 ,  G06F11/10 ,  G11C7/00 ,  G11C11/56 ,  G11C29/42 ,  G06F11/00

Abstract: The invention relates to a multi-level storage device comprising: at least a first plurality (CP) of cells (C-0...C-N), each adapted for storing an identical first number (greater than one) of binary data (B0...B7), and at least a corresponding second plurality (WP) of cells adapted for storing a second number of error check and correcting words (W-0...W-7) equal to said first number, said words (W-0...W-7) being respectively associated with sets of binary data, each comprising at least one binary data for each cell in said first plurality (CP). In this way, many of the known error correction algorithms can be applied to obtain comparable results to those provided by binary memories. In addition, where multi-level cells are used for storing the error check and correcting words, the device dimension requirements can also be comparable.