中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

32 records (took 0.022 seconds)

    13.
    发明专利
    未知

    公开(公告)号：DE69426487T2

    公开(公告)日：2001-06-07

    申请号：DE69426487

    申请日：1994-03-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAMPARDO GIOVANNI ,  DALLABORA MARCO

    IPC: G11C17/00 ,  G11C16/06 ,  G11C16/28 ,  G11C16/34

    Abstract: To reduce the supply voltage (VCC) of a nonvolatile memory (48), a read reference signal (H) is generated having a reference threshold value ranging between the maximum permissible threshold value for erased cells and the minimum permissible threshold value for written cells. To avoid reducing the maximum supply voltage, the characteristic (H) of the read reference signal is composed of two portions: a first portion (H1), ranging between the threshold value and a predetermined value (Vs), presents a slope lower than that of the characteristic (A, G) of the memory cells (50); and a second portion (H2), as of the predetermined value of the supply voltage, presents the same slope as the memory cells. The shifted-threshold, two-slope characteristic is achieved by means of virgin cells (11-13) so biased as to see bias voltages lower than the supply voltage.

    14.
    发明专利
    未知

    公开(公告)号：DE69515669T2

    公开(公告)日：2000-07-27

    申请号：DE69515669

    申请日：1995-10-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： TASSAN CASER FABIO ,  DALLABORA MARCO ,  DEFENDI MARCO

    IPC: H02M3/07

    Abstract: A negative charge pump circuit comprises: a plurality of charge pump stages (S1-S6), each charge pump stage (S1-S6) having an input node (I1-I6) and an output node (O1-O6) and comprising a pass transistor (P11-P16) and a first couplig capacitor (C21-C26), the pass transistor (P11-P16) having a first terminal connected to the input node (I1-I6), a second terminal connected to the output node (O1-O6) and a control terminal connected to an internal node (1-6) of the charge pump stage (S1-S6), said first coupling capacitor (C21-C26) having a first plate connected to said output node (O1-O6) and a second plate connected to a respective clock signal (A,B,C,D); negative voltage regulation means (7) for regulating a negative output voltage (V(O)) on an output node (O) of the negative charge pump circuit to provide a fixed negative voltage value. The negative charge pump circuit comprises at least one negative voltage limiting means (P7) electrically coupling said output node (O) of the negative charge pump circuit with the internal node (6) of the last charge pump stage (S6) of the negative charge pump circuit to limit the negative voltage on said internal node (6) and on the output node (O6) of said last charge pump stage (S6).

    16.
    发明专利
    未知

    公开(公告)号：DE69515669D1

    公开(公告)日：2000-04-20

    申请号：DE69515669

    申请日：1995-10-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： TASSAN CASER FABIO ,  DALLABORA MARCO ,  DEFENDI MARCO

    IPC: H02M3/07

    Abstract: A negative charge pump circuit comprises: a plurality of charge pump stages (S1-S6), each charge pump stage (S1-S6) having an input node (I1-I6) and an output node (O1-O6) and comprising a pass transistor (P11-P16) and a first couplig capacitor (C21-C26), the pass transistor (P11-P16) having a first terminal connected to the input node (I1-I6), a second terminal connected to the output node (O1-O6) and a control terminal connected to an internal node (1-6) of the charge pump stage (S1-S6), said first coupling capacitor (C21-C26) having a first plate connected to said output node (O1-O6) and a second plate connected to a respective clock signal (A,B,C,D); negative voltage regulation means (7) for regulating a negative output voltage (V(O)) on an output node (O) of the negative charge pump circuit to provide a fixed negative voltage value. The negative charge pump circuit comprises at least one negative voltage limiting means (P7) electrically coupling said output node (O) of the negative charge pump circuit with the internal node (6) of the last charge pump stage (S6) of the negative charge pump circuit to limit the negative voltage on said internal node (6) and on the output node (O6) of said last charge pump stage (S6).

    17.
    发明专利
    未知

    公开(公告)号：DE69325442D1

    公开(公告)日：1999-07-29

    申请号：DE69325442

    申请日：1993-03-18

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAMPARDO GIOVANNI ,  CRISENZA GIUSEPPE ,  DALLABORA MARCO

    IPC: G11C17/00 ,  G11C16/04 ,  G11C16/06 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    Abstract: To reduce the number of depleted cells (21) and the errors caused thereby, the memory array (20) comprises a number of groups of control transistors (23) relative to respective groups (22) of memory cells. The control transistors (23) of each group are NMOS transistors having the drain terminal connected to its own control line (BLP), and each of the control transistors of one group is relative to a row portion of the memory array (20): More specifically, each control transistor (23) presents the control gate connected to the respective word line (WL), and the source region connected to the source region of the cells (21) in the same row and in the same group (22).

Patent Agency Ranking