公开(公告)号：JP2001057087A

公开(公告)日：2001-02-27

申请号：JP2000227222

申请日：2000-07-27

Applicant: ST MICROELECTRONICS SRL

Inventor： BARTOLI SIMONE ,  BEDARIDA LORENZO ,  SALI MAURO ,  RUSSO ANTONIO

IPC: G11C16/02

Abstract: PROBLEM TO BE SOLVED: To obtain a memory having a burst mode reading function and a page mode reading function while erasing or programming one sector in a semiconductor memory having two or more memory sectors S1-S9. SOLUTION: This semiconductor memory is provided with first control circuit means 4, 6 for controlling the electrical change operation of contents of a memory. The first control circuit means 4 (6) can execute selectively the operation for changing electrically one content of a memory sector and can interrupt the execution so as to be possible to reading-access the other memory sectors. The memory is characterized by providing second control circuit means 8, 6 which can permit burst mode reading or page mode reading operation for reading contents of the other memory sectors.

公开(公告)号：JP2002230986A

公开(公告)日：2002-08-16

申请号：JP2002006161

申请日：2002-01-15

Applicant: ST MICROELECTRONICS SRL

Inventor： FRULIO MASSIMILIANO ,  VILLA CORRADO ,  BARTOLI SIMONE

IPC: G11C16/02 ,  G11C7/10 ,  G11C7/22 ,  G11C16/32

Abstract: PROBLEM TO BE SOLVED: To provide a nonvolatile memory which can perform synchronous reading with a frequency higher than a frequency which can be used now for data stored in a nonvolatile memory and which is operated by a burst reading mode. SOLUTION: This nonvolatile memory (10) is provided with an input pin (2) receiving an external clock signal supplied by a user, an input buffer (4) receiving the external clock signal and supplying an intermediate clock signal relating to the external clock signal and being delayed, and a delayed lock loop (12) receiving the intermediate clock signal and supplying the intermediate clock signal distributed in the nonvolatile memory and synchronizing with the external clock signal substantially.

公开(公告)号：EP0782268A3

公开(公告)日：1998-11-04

申请号：EP96830353

申请日：1996-06-20

Applicant: ST MICROELECTRONICS SRL

Inventor： VILLA CORRADO ,  BETTINI LUIGI ,  BARTOLI SIMONE

IPC: G11C5/14 ,  G11C16/12 ,  H03K17/687 ,  H03K17/693

CPC classification number: G11C5/143 ,  G11C16/12 ,  H03K17/6871 ,  H03K17/693

Abstract: A circuit for switching between supply voltages and in particular for non-volatile flash memory devices and of the type comprising a first and a second circuit branch each incorporating a pair of transistors (MA,MB;Mc,MD) connected in series provides that at least one branch (2) of the circuit be structured with a bridge circuit made up of P-channel MOS transistors. The bridge is made of a first (5) and a second (4) pairs of transistors (M1,M2,M3,M4) connected between a first supply voltage reference (SUPPLY1) and a common node (D). The first pair (5) comprises transistors (M1,M2) bigger than the transistors (M3,M4) of the second pair (4) while between the transistors (M3,M4) making up the second pair (4) is inserted a pair of resistors (R1,R2). Between the pair of resistors (R1,R2) there is an interconnection node (F) connected to a corresponding interconnection node (E) between the transistors (M1,M2) of the first pair (5).

公开(公告)号：DE69933203D1

公开(公告)日：2006-10-26

申请号：DE69933203

申请日：1999-07-21

Applicant: ST MICROELECTRONICS SRL

Inventor： BEDARIDA LORENZO ,  DISEGNI FABIO ,  DIMA VINCENZO ,  BARTOLI SIMONE

IPC: H03K17/06 ,  H03K17/30 ,  H03K19/00

Abstract: The present invention refers to a circuit disposal of a transistor shaped like a diode, in particular to a disposal able to reduce the threshold voltage of the transistor and equal to the difference of the threshold voltage of the used transistors in the circuit disposal. In an embodiment the circuit disposal comprises a first pMOS transistor (300) having a second pMOS transistor (301) shaped like a diode connected between the gate and the drain of the first transistor and a current generator (310) connected to the gates of the two transistors. Such a circuitry disposal it is also applicable to a nMOS transistor. From a general point of view this invention refers to a nMOS or pMOS transistor whose gate voltage is increased (for the nMOS transistors) or decreased (for the pMOS transistors) by using a circuit in series to the gate that provides an opportune delta of voltage.

公开(公告)号：DE69626376T2

公开(公告)日：2003-12-04

申请号：DE69626376

申请日：1996-04-30

Applicant: ST MICROELECTRONICS SRL

Inventor： DALLABORA MARCO ,  VILLA CORRADO ,  BARTOLI SIMONE ,  DEFENDI MARCO

IPC: G11C5/14 ,  G11C16/06

公开(公告)号：ITMI992487A1

公开(公告)日：2001-05-28

申请号：ITMI992487

申请日：1999-11-26

Applicant: ST MICROELECTRONICS SRL

Inventor： BEDARIDA LORENZO ,  BARTOLI SIMONE ,  BETTINI LUIGI

IPC: G11C7/06 ,  G11C7/22 ,  H03K3/011 ,  H03K3/355 ,  H03K5/04

Abstract: A pulse generator of a type that includes at least one current mirror connected between first and second voltage references and to at least one initiation terminal receiving a pulsive-type initiating signal, connected to a load terminal receiving a load signal, and connected to an output terminal providing an output signal. The pulse generator further includes at least one logic gate having one input terminal connected to an internal control circuit node of the current mirror, having another input terminal connected to receive the initiating signal, and having an output terminal connected to the output terminal of the pulse generator; at least one regulator circuit connected between the current mirror and the second voltage reference and feedback connected to the output terminal; and at least one conductive-type transistor connected between the current mirror and the regulator circuit; the output terminal of the pulse generator delivering a retarded pulsive-type output signal that is independent of the supply voltage and exhibits the same dependency on temperature as the regulator circuit.

公开(公告)号：DE69940473D1

公开(公告)日：2009-04-09

申请号：DE69940473

申请日：1999-11-25

Applicant: ST MICROELECTRONICS SRL

Inventor： BARTOLI SIMONE ,  GERACI ANTONINO ,  SALI MAURO ,  BEDARIDA LORENZO

IPC: G11C7/00 ,  G11C7/10

公开(公告)号：DE69923289D1

公开(公告)日：2005-02-24

申请号：DE69923289

申请日：1999-04-28

Applicant: ST MICROELECTRONICS SRL

Inventor： BARTOLI SIMONE ,  SALI MAURO ,  NAVA CLAUDIO ,  RUSSO ANTONIO

IPC: G11C5/00 ,  G11C5/06 ,  G11C7/10 ,  G11C7/00

Abstract: Semiconductor device comprising at least two pads (101, 102; 103, 104) for the input of external signals and/or for the output of signals from said semiconductor device, at least two uncoupling buffers (201, 202; 203, 204) each connected to each one of said pads, at least one multiplexer (10; 20) connected to said pads (101, 102; 103, 104) by means of said uncoupling buffers (201, 202; 203, 204) and at least one memory element (4; 5) suitable to generate a configuration signal (C ) operating on said multiplexer (10; 20) and said uncoupling buffers (201, 202; 203, 204) to selectively enable one or the other of said pads (101, 102; 103, 104).

公开(公告)号：IT1313873B1

公开(公告)日：2002-09-24

申请号：ITMI992372

申请日：1999-11-12

Applicant: ST MICROELECTRONICS SRL

Inventor： BARTOLI SIMONE ,  BEDARIDA LORENZO ,  SALI MAURO ,  RUSSO ANTONIO

IPC: G11C5/14 ,  G11C8/12 ,  G11C16/12 ,  G11C16/16 ,  G11C16/30

公开(公告)号：ITMI992487D0

公开(公告)日：1999-11-26

申请号：ITMI992487

申请日：1999-11-26

Applicant: ST MICROELECTRONICS SRL

Inventor： BEDARIDA LORENZO ,  BARTOLI SIMONE ,  BETTINI LUIGI

IPC: G11C7/06 ,  G11C7/22 ,  H03K3/011 ,  H03K3/355 ,  H03K5/04

Abstract: A pulse generator of a type that includes at least one current mirror connected between first and second voltage references and to at least one initiation terminal receiving a pulsive-type initiating signal, connected to a load terminal receiving a load signal, and connected to an output terminal providing an output signal. The pulse generator further includes at least one logic gate having one input terminal connected to an internal control circuit node of the current mirror, having another input terminal connected to receive the initiating signal, and having an output terminal connected to the output terminal of the pulse generator; at least one regulator circuit connected between the current mirror and the second voltage reference and feedback connected to the output terminal; and at least one conductive-type transistor connected between the current mirror and the regulator circuit; the output terminal of the pulse generator delivering a retarded pulsive-type output signal that is independent of the supply voltage and exhibits the same dependency on temperature as the regulator circuit.