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    Supply voltages switch circuit
    1.
    发明公开
    Supply voltages switch circuit 失效
    电路的工作电压

    公开(公告)号：EP0782268A3

    公开(公告)日：1998-11-04

    申请号：EP96830353

    申请日：1996-06-20

    Applicant: ST MICROELECTRONICS SRL

    Inventor： VILLA CORRADO ,  BETTINI LUIGI ,  BARTOLI SIMONE

    IPC: G11C5/14 ,  G11C16/12 ,  H03K17/687 ,  H03K17/693

    CPC classification number: G11C5/143 ,  G11C16/12 ,  H03K17/6871 ,  H03K17/693

    Abstract: A circuit for switching between supply voltages and in particular for non-volatile flash memory devices and of the type comprising a first and a second circuit branch each incorporating a pair of transistors (MA,MB;Mc,MD) connected in series provides that at least one branch (2) of the circuit be structured with a bridge circuit made up of P-channel MOS transistors. The bridge is made of a first (5) and a second (4) pairs of transistors (M1,M2,M3,M4) connected between a first supply voltage reference (SUPPLY1) and a common node (D). The first pair (5) comprises transistors (M1,M2) bigger than the transistors (M3,M4) of the second pair (4) while between the transistors (M3,M4) making up the second pair (4) is inserted a pair of resistors (R1,R2). Between the pair of resistors (R1,R2) there is an interconnection node (F) connected to a corresponding interconnection node (E) between the transistors (M1,M2) of the first pair (5).

    4.
    发明专利
    未知

    公开(公告)号：DE69627350D1

    公开(公告)日：2003-05-15

    申请号：DE69627350

    申请日：1996-11-27

    Applicant: ST MICROELECTRONICS SRL

    Inventor： VILLA CORRADO ,  DEFENDI MARCO ,  BETTINI LUIGI

    IPC: G11C11/41 ,  G11C8/18 ,  G11C8/00

    Abstract: The invention relates to a method and a circuit for generating a pulse synchronization signal (ATD) in order to control the reading phase of memorycells in semiconductor integrated, electronic memory devices. The pulse signal (ATD) is generated upon sensing a change in logic state on at least one of a plurality of address input terminals (PAD) of the memory cells to also generate an equalization signal (EQLZ) for a sense amplifier. The logic state of said pulse signal (ATD) is re-acknowledged by a fed-back response having a predetermined delay and being generated upon reception of a corresponding signal to said equalization signal (EQLZ). To this aim, a re-acknowledge circuit portion (15) is provided which is input a corresponding signal to the equalization signal (EQLZ) and feedback connected to the output node (12) to drive the discharging of the node (12) with a predetermined delay from the reception of the input signal.

    7.
    发明专利
    未知

    公开(公告)号：DE69516883T2

    公开(公告)日：2000-10-05

    申请号：DE69516883

    申请日：1995-12-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： VILLA CORRADO ,  DEFENDI MARCO ,  BETTINI LUIGI

    IPC: G11C16/16 ,  G11C11/00

    Abstract: The invention relates to a method of erasing an electrically programmable non-volatile memory device constructed as a multi-sector matrix memory and being of the type with an erase algorithm integrated into the device. The method comprises the following steps: erasing some or all of the matrix sectors in parallel; subsequently reading and checking each erased sector; storing the address of a sector being checked when the issue of a check is unfavorable; carrying out a fresh parallel erasing step; and starting a new reading/checking step from the sector that has checked unfavorably.

    8.
    发明专利
    未知

    公开(公告)号：DE69516883D1

    公开(公告)日：2000-06-15

    申请号：DE69516883

    申请日：1995-12-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： VILLA CORRADO ,  DEFENDI MARCO ,  BETTINI LUIGI

    IPC: G11C16/16 ,  G11C11/00

    Abstract: The invention relates to a method of erasing an electrically programmable non-volatile memory device constructed as a multi-sector matrix memory and being of the type with an erase algorithm integrated into the device. The method comprises the following steps: erasing some or all of the matrix sectors in parallel; subsequently reading and checking each erased sector; storing the address of a sector being checked when the issue of a check is unfavorable; carrying out a fresh parallel erasing step; and starting a new reading/checking step from the sector that has checked unfavorably.

    9.
    发明专利
    未知

    公开(公告)号：ITMI992487D0

    公开(公告)日：1999-11-26

    申请号：ITMI992487

    申请日：1999-11-26

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BEDARIDA LORENZO ,  BARTOLI SIMONE ,  BETTINI LUIGI

    IPC: G11C7/06 ,  G11C7/22 ,  H03K3/011 ,  H03K3/355 ,  H03K5/04

    Abstract: A pulse generator of a type that includes at least one current mirror connected between first and second voltage references and to at least one initiation terminal receiving a pulsive-type initiating signal, connected to a load terminal receiving a load signal, and connected to an output terminal providing an output signal. The pulse generator further includes at least one logic gate having one input terminal connected to an internal control circuit node of the current mirror, having another input terminal connected to receive the initiating signal, and having an output terminal connected to the output terminal of the pulse generator; at least one regulator circuit connected between the current mirror and the second voltage reference and feedback connected to the output terminal; and at least one conductive-type transistor connected between the current mirror and the regulator circuit; the output terminal of the pulse generator delivering a retarded pulsive-type output signal that is independent of the supply voltage and exhibits the same dependency on temperature as the regulator circuit.

    10.
    发明专利
    未知

    公开(公告)号：IT1314090B1

    公开(公告)日：2002-12-04

    申请号：ITMI992487

    申请日：1999-11-26

    Applicant: ST MICROELECTRONICS SRL

    Inventor： DIMA VINCENZO ,  BEDARIDA LORENZO ,  BETTINI LUIGI

    IPC: G11C7/06 ,  G11C7/22 ,  H03K3/011 ,  H03K3/355 ,  H03K5/04

    Abstract: A pulse generator of a type that includes at least one current mirror connected between first and second voltage references and to at least one initiation terminal receiving a pulsive-type initiating signal, connected to a load terminal receiving a load signal, and connected to an output terminal providing an output signal. The pulse generator further includes at least one logic gate having one input terminal connected to an internal control circuit node of the current mirror, having another input terminal connected to receive the initiating signal, and having an output terminal connected to the output terminal of the pulse generator; at least one regulator circuit connected between the current mirror and the second voltage reference and feedback connected to the output terminal; and at least one conductive-type transistor connected between the current mirror and the regulator circuit; the output terminal of the pulse generator delivering a retarded pulsive-type output signal that is independent of the supply voltage and exhibits the same dependency on temperature as the regulator circuit.

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