中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

16 records (took 0.023 seconds)

    11.
    发明专利
    未知

    公开(公告)号：DE69515669D1

    公开(公告)日：2000-04-20

    申请号：DE69515669

    申请日：1995-10-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： TASSAN CASER FABIO ,  DALLABORA MARCO ,  DEFENDI MARCO

    IPC: H02M3/07

    Abstract: A negative charge pump circuit comprises: a plurality of charge pump stages (S1-S6), each charge pump stage (S1-S6) having an input node (I1-I6) and an output node (O1-O6) and comprising a pass transistor (P11-P16) and a first couplig capacitor (C21-C26), the pass transistor (P11-P16) having a first terminal connected to the input node (I1-I6), a second terminal connected to the output node (O1-O6) and a control terminal connected to an internal node (1-6) of the charge pump stage (S1-S6), said first coupling capacitor (C21-C26) having a first plate connected to said output node (O1-O6) and a second plate connected to a respective clock signal (A,B,C,D); negative voltage regulation means (7) for regulating a negative output voltage (V(O)) on an output node (O) of the negative charge pump circuit to provide a fixed negative voltage value. The negative charge pump circuit comprises at least one negative voltage limiting means (P7) electrically coupling said output node (O) of the negative charge pump circuit with the internal node (6) of the last charge pump stage (S6) of the negative charge pump circuit to limit the negative voltage on said internal node (6) and on the output node (O6) of said last charge pump stage (S6).

    12.
    发明专利
    未知

    公开(公告)号：DE69928514D1

    公开(公告)日：2005-12-29

    申请号：DE69928514

    申请日：1999-06-25

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BEDARIDA LORENZO ,  DIMA VINCENZO ,  BRANI FRANCESCO ,  DEFENDI MARCO

    IPC: G11C7/14 ,  G11C16/28

    Abstract: A circuit for reading a semiconductor memory device comprises at least one global circuit (1) for generating a global reference signal (RIFN) for a respective plurality of cell-reading circuits (SA1-SAn) disposed locally in the memory device. The circuit comprises at least one circuit (51-5an) for replicating the reference signal (RIFN) locally in order to generate a local reference signal (MAT11-MAT1n) to be supplied to at least one respective cell-reading circuit (SA1-SAn).

    15.
    发明专利
    未知

    公开(公告)号：DE69627350D1

    公开(公告)日：2003-05-15

    申请号：DE69627350

    申请日：1996-11-27

    Applicant: ST MICROELECTRONICS SRL

    Inventor： VILLA CORRADO ,  DEFENDI MARCO ,  BETTINI LUIGI

    IPC: G11C11/41 ,  G11C8/18 ,  G11C8/00

    Abstract: The invention relates to a method and a circuit for generating a pulse synchronization signal (ATD) in order to control the reading phase of memorycells in semiconductor integrated, electronic memory devices. The pulse signal (ATD) is generated upon sensing a change in logic state on at least one of a plurality of address input terminals (PAD) of the memory cells to also generate an equalization signal (EQLZ) for a sense amplifier. The logic state of said pulse signal (ATD) is re-acknowledged by a fed-back response having a predetermined delay and being generated upon reception of a corresponding signal to said equalization signal (EQLZ). To this aim, a re-acknowledge circuit portion (15) is provided which is input a corresponding signal to the equalization signal (EQLZ) and feedback connected to the output node (12) to drive the discharging of the node (12) with a predetermined delay from the reception of the input signal.

Patent Agency Ranking