公开(公告)号：ITMI20001315A1

公开(公告)日：2001-12-13

申请号：ITMI20001315

申请日：2000-06-13

Applicant: ST MICROELECTRONICS SRL

Inventor： BEDARIDA LORENZO ,  GERACI ANTONINO ,  LISI CARLO ,  DIMA VINCENZO

IPC: G11C16/28

Abstract: The present invention relates a circuit arrangement for the lowering of the threshold voltage of a diode configured transistor comprising a mirror transistor, a first transistor and a second transistor, said mirror transistor and said first transistor having in common the gate electrodes in a circuit node, said second transistor being connected in a transdiode configuration and placed between the gate electrode and the drain electrode of said first transistor, and a current source being connected to the gate electrode of said first transistor and to the drain electrode of said second transistor, characterized by comprising a third transistor which is configured to receive a switching signal at its gate electrode and is connected between the drain and the gate electrode of said first transistor.

公开(公告)号：ITTO20020566A1

公开(公告)日：2003-12-29

申请号：ITTO20020566

申请日：2002-06-28

Applicant: ST MICROELECTRONICS SRL

Inventor： DEL GATTO NICOLA ,  DIMA VINCENZO ,  POIDOMANI CARLA ,  CHIAVETTA CARMELO

IPC: G05F3/24 ,  G05F3/26

Abstract: A voltage regulator with quick response includes: an output terminal supplying a regulated voltage; and at least a first boost circuit, controlled for alternately accumulating a first charge in a first operating condition and supplying the first charge to the output terminal in a second operating condition. In addition, the first boost circuit is provided with a compensation stage supplying the output terminal with a second charge substantially equal to the first charge, when the first boost circuit is in the first operating condition.

公开(公告)号：ITMI992576A1

公开(公告)日：2001-06-13

申请号：ITMI992576

申请日：1999-12-13

Applicant: ST MICROELECTRONICS SRL

Inventor： BEDARIDA LORENZO ,  BARTOLI SIMONE ,  DIMA VINCENZO ,  GERACI ANTONINO

IPC: G05F3/24

Abstract: An output buffer device having first and second supply voltage references, the first voltage reference being lower in value than the second voltage reference. The output buffer device includes first and second complementary MOS transistors, which transistors are connected in series together between one of the supply voltage references and a further voltage reference, have gate terminals connected together and to an input terminal of this buffer device, and have drain terminals connected together and to an output terminal of the buffer device. Advantageously, the first transistor is connected to the first supply voltage reference. Furthermore, the output buffer device comprises at least one additional drive MOS transistor of the same type as the first MOS transistor and placed between the second supply voltage reference and the output terminal of the buffer device.

公开(公告)号：ITMI992576D0

公开(公告)日：1999-12-13

申请号：ITMI992576

申请日：1999-12-13

Applicant: ST MICROELECTRONICS SRL

Inventor： BEDARIDA LORENZO ,  BARTOLI SIMONE ,  DIMA VINCENZO ,  GERACI ANTONINO

IPC: G05F3/24

Abstract: An output buffer device having first and second supply voltage references, the first voltage reference being lower in value than the second voltage reference. The output buffer device includes first and second complementary MOS transistors, which transistors are connected in series together between one of the supply voltage references and a further voltage reference, have gate terminals connected together and to an input terminal of this buffer device, and have drain terminals connected together and to an output terminal of the buffer device. Advantageously, the first transistor is connected to the first supply voltage reference. Furthermore, the output buffer device comprises at least one additional drive MOS transistor of the same type as the first MOS transistor and placed between the second supply voltage reference and the output terminal of the buffer device.

公开(公告)号：DE69739825D1

公开(公告)日：2010-05-12

申请号：DE69739825

申请日：1997-09-24

Applicant: ST MICROELECTRONICS SRL

Inventor： BARTOLI SIMONE ,  DIMA VINCENZO ,  SALI MAURO LUIGI

IPC: G11C8/00 ,  G11C8/12 ,  G11C16/06 ,  G11C16/08

公开(公告)号：DE69928514D1

公开(公告)日：2005-12-29

申请号：DE69928514

申请日：1999-06-25

Applicant: ST MICROELECTRONICS SRL

Inventor： BEDARIDA LORENZO ,  DIMA VINCENZO ,  BRANI FRANCESCO ,  DEFENDI MARCO

IPC: G11C7/14 ,  G11C16/28

Abstract: A circuit for reading a semiconductor memory device comprises at least one global circuit (1) for generating a global reference signal (RIFN) for a respective plurality of cell-reading circuits (SA1-SAn) disposed locally in the memory device. The circuit comprises at least one circuit (51-5an) for replicating the reference signal (RIFN) locally in order to generate a local reference signal (MAT11-MAT1n) to be supplied to at least one respective cell-reading circuit (SA1-SAn).

公开(公告)号：IT1318013B1

公开(公告)日：2003-07-21

申请号：ITMI20001315

申请日：2000-06-13

Applicant: ST MICROELECTRONICS SRL

Inventor： LISI CARLO ,  BEDARIDA LORENZO ,  GERACI ANTONINO ,  DIMA VINCENZO

IPC: G11C16/28

Abstract: The present invention relates a circuit arrangement for the lowering of the threshold voltage of a diode configured transistor comprising a mirror transistor, a first transistor and a second transistor, said mirror transistor and said first transistor having in common the gate electrodes in a circuit node, said second transistor being connected in a transdiode configuration and placed between the gate electrode and the drain electrode of said first transistor, and a current source being connected to the gate electrode of said first transistor and to the drain electrode of said second transistor, characterized by comprising a third transistor which is configured to receive a switching signal at its gate electrode and is connected between the drain and the gate electrode of said first transistor.

公开(公告)号：IT1314122B1

公开(公告)日：2002-12-04

申请号：ITMI992576

申请日：1999-12-13

Applicant: ST MICROELECTRONICS SRL

Inventor： DIMA VINCENZO ,  BEDARIDA LORENZO ,  GERACI ANTONINO ,  BARTOLI SIMONE

IPC: G05F3/24

Abstract: An output buffer device having first and second supply voltage references, the first voltage reference being lower in value than the second voltage reference. The output buffer device includes first and second complementary MOS transistors, which transistors are connected in series together between one of the supply voltage references and a further voltage reference, have gate terminals connected together and to an input terminal of this buffer device, and have drain terminals connected together and to an output terminal of the buffer device. Advantageously, the first transistor is connected to the first supply voltage reference. Furthermore, the output buffer device comprises at least one additional drive MOS transistor of the same type as the first MOS transistor and placed between the second supply voltage reference and the output terminal of the buffer device.

公开(公告)号：DE69933203D1

公开(公告)日：2006-10-26

申请号：DE69933203

申请日：1999-07-21

Applicant: ST MICROELECTRONICS SRL

Inventor： BEDARIDA LORENZO ,  DISEGNI FABIO ,  DIMA VINCENZO ,  BARTOLI SIMONE

IPC: H03K17/06 ,  H03K17/30 ,  H03K19/00

Abstract: The present invention refers to a circuit disposal of a transistor shaped like a diode, in particular to a disposal able to reduce the threshold voltage of the transistor and equal to the difference of the threshold voltage of the used transistors in the circuit disposal. In an embodiment the circuit disposal comprises a first pMOS transistor (300) having a second pMOS transistor (301) shaped like a diode connected between the gate and the drain of the first transistor and a current generator (310) connected to the gates of the two transistors. Such a circuitry disposal it is also applicable to a nMOS transistor. From a general point of view this invention refers to a nMOS or pMOS transistor whose gate voltage is increased (for the nMOS transistors) or decreased (for the pMOS transistors) by using a circuit in series to the gate that provides an opportune delta of voltage.

公开(公告)号：IT1314090B1

公开(公告)日：2002-12-04

申请号：ITMI992487

申请日：1999-11-26

Applicant: ST MICROELECTRONICS SRL

Inventor： DIMA VINCENZO ,  BEDARIDA LORENZO ,  BETTINI LUIGI

IPC: G11C7/06 ,  G11C7/22 ,  H03K3/011 ,  H03K3/355 ,  H03K5/04

Abstract: A pulse generator of a type that includes at least one current mirror connected between first and second voltage references and to at least one initiation terminal receiving a pulsive-type initiating signal, connected to a load terminal receiving a load signal, and connected to an output terminal providing an output signal. The pulse generator further includes at least one logic gate having one input terminal connected to an internal control circuit node of the current mirror, having another input terminal connected to receive the initiating signal, and having an output terminal connected to the output terminal of the pulse generator; at least one regulator circuit connected between the current mirror and the second voltage reference and feedback connected to the output terminal; and at least one conductive-type transistor connected between the current mirror and the regulator circuit; the output terminal of the pulse generator delivering a retarded pulsive-type output signal that is independent of the supply voltage and exhibits the same dependency on temperature as the regulator circuit.