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    12.
    发明专利
    未知

    公开(公告)号：DE69328253D1

    公开(公告)日：2000-05-04

    申请号：DE69328253

    申请日：1993-12-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MACCARRONE MARCO ,  OLIVO MARCO ,  GOLLA CARLA ,  PADOAN SILVIA

    IPC: G11C5/14 ,  G11C16/06 ,  G11C17/00 ,  G11C16/30

    Abstract: A voltage regulator for programming non-volatile memory cells, which comprises an amplifier stage (4) being powered between a first (VPP) and a second (GND) voltage reference and having a first input terminal connected to a resistive divider (2) of the first reference voltage (VPP) and an output terminal fed back to said input through a current mirror (3), and a source-follower transistor (MOUT) controlled by the output and connected to the cells through a programming line (VP). Also provided is a MOS transistor (MG2) which connects to ground the programming line (VP) and a corresponding resistive path (7) connected between the current mirror (3) and the second voltage reference (GND).

    13.
    发明专利
    未知

    公开(公告)号：DE69430806T2

    公开(公告)日：2002-12-12

    申请号：DE69430806

    申请日：1994-12-05

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GOLLA CARLA ,  VESPI WILLIAM

    IPC: G05F1/46 ,  G11C5/14 ,  H02M3/07 ,  G05F1/00 ,  G05F3/20

    Abstract: A charge pump voltage booster circuit (1) with control feedback of the type comprising an output line (2) connected to a load and on which is produced an output voltage (Vboost) boosted in relation to a supply voltage (Vcc) and a feedback loop incorporating a charge pump (10) connected to said line (2) and a control logic circuit (8) of said pump (10) interlocked with a comparator (7) having an input connected to the line (2) comprises also an auxiliary charge pump (11) connected in turn to said line (2) and designed to supply a quantity of current greater than or equal to the leakage currents of the load in stand-by condition. The auxiliary pump (11) has current consumption much lower than that of the main charge pump. In addition, upon emerging from the off state there is provided starting of the main charge pump (10) for a brief time period sufficient to take the booster output to a sufficient value.

    14.
    发明专利
    未知

    公开(公告)号：DE69430806D1

    公开(公告)日：2002-07-18

    申请号：DE69430806

    申请日：1994-12-05

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GOLLA CARLA ,  VESPI WILLIAM

    IPC: G05F1/46 ,  G11C5/14 ,  H02M3/07 ,  G05F1/00 ,  G05F3/20

    Abstract: A charge pump voltage booster circuit (1) with control feedback of the type comprising an output line (2) connected to a load and on which is produced an output voltage (Vboost) boosted in relation to a supply voltage (Vcc) and a feedback loop incorporating a charge pump (10) connected to said line (2) and a control logic circuit (8) of said pump (10) interlocked with a comparator (7) having an input connected to the line (2) comprises also an auxiliary charge pump (11) connected in turn to said line (2) and designed to supply a quantity of current greater than or equal to the leakage currents of the load in stand-by condition. The auxiliary pump (11) has current consumption much lower than that of the main charge pump. In addition, upon emerging from the off state there is provided starting of the main charge pump (10) for a brief time period sufficient to take the booster output to a sufficient value.

    15.
    发明专利
    未知

    公开(公告)号：DE69428423D1

    公开(公告)日：2001-10-31

    申请号：DE69428423

    申请日：1994-02-21

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GOLLA CARLA ,  PADOAN SILVIA ,  OLIVO MARCO

    IPC: G11C17/00 ,  G11C16/06 ,  G11C16/14 ,  G11C16/16

    Abstract: A regulating circuit for discharging non-volatile memory cells (5) in an electrically programmable memory device, of the type which comprises: at least one switch connected between a programming voltage reference (VPP) and a line (SCR) shared by the source terminals of the transistors forming said memory cells (5), and at least one discharge connection between said common line (SCR) to the source terminals and a ground voltage reference (GND), further comprises a second connection to ground of the line (SCR) in which a current (Is) generator (G) is connected and a normally open switch (I1). Also provided is a logic circuit (3) connected to the line (SRC) to compare the voltage value present on the latter with a predetermined value, and to output a control signal for causing the switch (I1) to make. This solution allows a slow discharging phase of the line (SRC) to be effected at the end of the erasing phase.

    17.
    发明专利
    未知

    公开(公告)号：DE69325277D1

    公开(公告)日：1999-07-15

    申请号：DE69325277

    申请日：1993-12-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PADOAN SILVIA ,  OLIVO MARCO ,  GOLLA CARLA

    IPC: G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  G11C16/30

    Abstract: A circuit for detecting a threshold voltage in storage devices integrated to a semiconductor, for which a power supply above a certain value is provided, is of the type which comprises a comparator (3) connected between a voltage supply line (2) and a signal ground (GND) and having a first or reference input (I1) and a second or signal input (I2), and comprises a generator (8) of a stable voltage reference (RIF) having an output connected to the first input (I1) and a divider (9) of a supply voltage (Vdd) connected to the second input (I2) of the comparator (3). A circuit means is arranged to feed the voltage line (2) with the higher of the supply voltage (Vdd) value and the value of a programming voltage (Vpp) of the storage device.

    20.
    发明专利
    未知

    公开(公告)号：DE69624230D1

    公开(公告)日：2002-11-14

    申请号：DE69624230

    申请日：1996-07-24

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAMPARDO GIOVANNI ,  ZANARDI STEFANO ,  GOLLA CARLA

    IPC: H03K19/003 ,  H03K17/00

    Abstract: An output stage (1) for electronic circuits (2) with high voltage tolerance and of the type comprising an output buffer made up of a complementary transistor pair (Pu,Nu) comprising a P-channel MOS pull-up transistor (Pu) and an N-channel MOS pull-down transistor. The transistors are connected together to make up an output terminal (U) of the stage which comprises in addition a switch (6) having an input (8) connected to the output terminal (U) of the stage and an output (9) connected to the control terminal of the pull-up transistor to drive said control terminal in a state of extinction of the output buffer.

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