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    SWITCHING CAPACITOR CIRCUIT AND SWITCHING CAPACITOR FILTER USING IT
    11.
    发明专利
    SWITCHING CAPACITOR CIRCUIT AND SWITCHING CAPACITOR FILTER USING IT 失效

    公开(公告)号：JPH0846488A

    公开(公告)日：1996-02-16

    申请号：JP9729995

    申请日：1995-04-21

    Applicant: ST MICROELECTRONICS SRL

    Inventor： NICOLLINI GERMANO ,  NAGARI ANGELO

    IPC: G11C27/02 ,  H03F3/00 ,  H03H19/00 ,  H03K5/24

    Abstract: PURPOSE: To provide a switching capacitor circuit lowering harmonic wave distortion without considerably increasing the complexity of circuit and the area required for integration as an integrated circuit. CONSTITUTION: This circuit has one operational amplifier (OA) 2 at least having 1st and 2nd input terminals at least and a 1st output terminal at least and connecting the 1st input terminal to a 1st reference potential and at this switching capacitor circuit provided with one negative feedback network at least provided with a capacitor C2 at the OA2 while having the 2nd input terminal through a switch SW1, the 1st terminal alternately connected to the 1st reference potential and the 2nd terminal connected through a switch SW2 alternately to a circuit node A connected to the 1st input and output terminals of OA2, a capacitor CX is provided at least while being connected between the circuit node A and a 2nd reference potential.

    BUFFER DEVICE FOR SWITCHED CAPACITY CIRCUIT
    13.
    发明申请
    BUFFER DEVICE FOR SWITCHED CAPACITY CIRCUIT 审中-公开
    缓冲器装置的开关电容电路

    公开(公告)号：WO2008023395A8

    公开(公告)日：2008-07-03

    申请号：PCT/IT2006000628

    申请日：2006-08-25

    Applicant: ST MICROELECTRONICS SRL ,  ZAMPROGNO MARCO ,  NICOLLINI GERMANO ,  MINUTI ALBERTO

    Inventor： ZAMPROGNO MARCO ,  NICOLLINI GERMANO ,  MINUTI ALBERTO

    IPC: H03F3/00

    CPC classification number: H03F1/3211 ,  H03F3/005 ,  H03F3/45475 ,  H03F3/45977 ,  H03F2203/45101 ,  H03F2203/45136 ,  H03F2203/45212 ,  H03F2203/45514

    Abstract: An integrated buffer device (2) for a switched capacity circuit is described, comprising: - a buffer (7) having an output (OUT) for an output voltage dependent upon an input voltage (VIN) that can be supplied by a source (1) to the buffer device; - a capacitative switching component (C I ) that can be switched between a first and second condition in which it is connected, respectively, to the source and to the buffer to transfer the input voltage onto the output; said component being provided with a terminal (N2) having an associated stray capacity (C pi ). The device also comprises a charging and discharging device (SW CPIR , SW G ) configured to pre- charge the stray capacity at a reference voltage (REFM) before taking up the second condition and to pre-discharge the stray capacity before taking up the first condition.

    Abstract translation: 描述了一种用于开关电容电路的集成缓冲器件（2），包括： - 缓冲器（7），其具有用于依赖于输入电压（VIN）的输出电压的输出（OUT），该输出电压可以由源 ）到缓冲设备; - 可以在第一和第二条件之间切换的电容性开关元件（C I ），在所述第一和第二条件下，所述第一和第二条件分别连接到源极和缓冲器以将输入电压传输到输出端; 所述组件设置有具有相关寄生容量（C pi ）的终端（N2）。 该器件还包括一个充电和放电装置（SW CPIR ，SW G ），用于在占用第二个参考电压（REFM）前对杂散电容进行预充电 条件并在占用第一条件之前预先放电杂散容量。

    17.
    发明专利
    未知

    公开(公告)号：DE602007005766D1

    公开(公告)日：2010-05-20

    申请号：DE602007005766

    申请日：2007-02-23

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CONFALONIERI PIERANGELO ,  MARTIGNONE RICCARDO ,  NICOLLINI GERMANO

    IPC: H03H1/02 ,  H03H7/01

    Abstract: A calibration circuit (30) for calibrating an adjustable capacitance (C var (REG_BUS)) of a circuit (31) having a time constant depending on said adjustable capacitance, the calibration circuit (30) being such as to output a calibration signal (REG_BUS) carrying information for calibrating said capacitance ((C var (REG_BUS)) and including a calibration loop (U_CV, CMP, TG_SAR), suitable to carry out a calibration cycle (C_LOOP) in several sequential steps (St_1, ..., St4), comprising: - a controllable capacitance unit (U_CV) suitable to receive a control signal (SAR_BUS) at the beginning of a calibration step and including an array of switched capacitors (C_AR1) that can be selectively activated by the control signal to be connected to a first common node (N_u) having, at the end of an integration interval (P2), a voltage value (VRC) depending on the total capacitance value of the activated capacitors; - an assessment unit (CMP) suitable to compare this voltage value (VRC) with a reference voltage to output a logic signal (OUT_CMP) that, based on the comparison result can be subjected to a transition between first and second logic levels; - a control and timing unit (TG_SAR) suitable to receive the logic signal (OUT_CMP) and to change the control signal (SAR_BUS) based thereon, in order to carry out a subsequent calibration step, characterized in that in said calibration step is provided, at the end of said integration interval (P2) a comparison interval (P3) of a preset duration, which allows a transition (tl,t4) of the logic signal (OUT_CMP) to occur prior to the beginning of said consecutive calibration step.

    18.
    发明专利
    未知

    公开(公告)号：DE602005014471D1

    公开(公告)日：2009-06-25

    申请号：DE602005014471

    申请日：2005-05-19

    Applicant: ST MICROELECTRONICS SRL

    Inventor： NICOLLINI GERMANO ,  CONFALONIERI PIERANGELO ,  MARTIGNONE RICCARDO

    IPC: H04M1/74 ,  H03M1/74 ,  H04B1/707

    Abstract: There is described a wide-band transmission system, particularly for employment in cellular telephony systems that adopt the WCDMA standard. The system comprises means for generating two digital signals containing information to be transmitted, means for converting into analog form the two signals comprising, for each signal to be converted, a digital-analog converter (DAC) followed by a low-pass filter (LOW-PASS), means for modulating both in phase and in quadrature a radio frequency carrier with the two signals issuing from the low-pass filters (LOW-PASS), and means for transmitting the modulated carrier in accordance with a predetermined emission mask. If the system is to be capable of being integrated into an area of small extent and is to have a low current consumption, the low-pass filter (LOW-PASS) is an active filter of the second order continuous in time and current-coupled to the output of the digital-analog converter (DAC) and the digital-analog converter (DAC) is a converter of the current-steering type functioning at a sampling frequency greater than the Nyquist frequency by at least as much as is necessary to respect the predetermined emission mask.

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