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    ROW-ADDRESS DECODING AND SELECTION CIRCUIT
    11.
    发明专利
    ROW-ADDRESS DECODING AND SELECTION CIRCUIT 失效

    公开(公告)号：JPH07201193A

    公开(公告)日：1995-08-04

    申请号：JP31188894

    申请日：1994-12-15

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GOLLA CARLA MARIA ,  OLIVO MARCO

    IPC: G11C17/00 ,  G11C8/12 ,  G11C16/06 ,  G11C16/08 ,  G11C29/00 ,  G11C29/04

    Abstract: PURPOSE: To provide a two rows address decoding/selection circuit for a non- volatile memory device, which has redundancy, which can electrically be deleted and into which data can be written. CONSTITUTION: Circuit blocks PGO-PG15 generate carry-out signals CO0-C015 which are supplied to the carry-in terminals CI0-C115 of a circuit block in a next stage and are activated when selection signals PO-P15 are activated. The first circuit block PG0 has has the carry-in terminal CI0 connected to reference potential GND. The circuit blocks PG0-PG15 supply control signals E activated by the control circuit 6 of the memory device when defective rows WL0-WL15 are addressed in prior to the electrical deletion of the memory device during a preprogramming operation. When carry-out signals CO-C015 are activated, the selection signals PO-P15 are activated and the two adjacent rows WL0-WL15 can be selected.

    CIRCUIT AND METHOD FOR GENERATING RESET SIGNAL
    14.
    发明专利
    CIRCUIT AND METHOD FOR GENERATING RESET SIGNAL 失效

    公开(公告)号：JPH07253830A

    公开(公告)日：1995-10-03

    申请号：JP11895

    申请日：1995-01-04

    Applicant: ST MICROELECTRONICS SRL

    Inventor： OLIVO MARCO ,  PADOAN SILVIA

    IPC: G11C17/00 ,  G06F1/24 ,  G11C16/06 ,  G11C16/30

    Abstract: PURPOSE: To execute control by means of a reset signal even when a power supply voltage is raised to a steady state value from zero. CONSTITUTION: An electrically programmable nonvolatile storage device 1 is constituted of a memory matrix 2 to which a power supply voltage Vcc and a programming voltage Vpp are supplied, a control logic circuit 3, and a threshold detecting circuit 5 which is constituted to detect the drop of the voltage Vcc and supplies a signal obtained as the function of variation between reset signals POR generated during the power supply rising period of the storage device 1 to the logic circuit 3.

    THRESHOLD DETECTOR CIRCUIT
    15.
    发明专利
    THRESHOLD DETECTOR CIRCUIT 失效

    公开(公告)号：JPH07249296A

    公开(公告)日：1995-09-26

    申请号：JP11795

    申请日：1995-01-04

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PADOAN SILVIA ,  OLIVO MARCO ,  GOLLA CARLA

    IPC: G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  G11C16/30

    Abstract: PURPOSE: To improve a stability of tripping threshold value of an output signal and operating range controllability by providing a threshold value detection circuit for detecting a low threshold voltage without being affected by the change of a reference voltage. CONSTITUTION: A comparator 3 has a stable reference voltage RIF to be held at an input terminal regardless of supply voltage and temperature. By using this stable voltage reference, the tripping threshold value of the comparator 3 can be exactly set. In a normal operating state, an output signal VCCLOW from the comparator 3 is zero but when a supply voltage Vdd is reduced lower than a tripping level or a concerned circuit is turned into about 2.5V or deep power down state, for example, the voltage is increased to a voltage value Vu on a power supply line 2. Respective elements are provided with MOS transistors to be controlled by a signal PWDN according to the negative logic obtained from the external signal PWD through a negator N1. Thus, the stability of the tripping threshold value and the operation controllability can be improved.

    ANTINOISE AND AUTOMATIC STANDBY MEMORY STRUCTURE
    16.
    发明专利
    ANTINOISE AND AUTOMATIC STANDBY MEMORY STRUCTURE 失效

    公开(公告)号：JPH06342596A

    公开(公告)日：1994-12-13

    申请号：JP22458792

    申请日：1992-07-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  OLIVO MARCO

    IPC: G11C11/417 ,  G11C7/10 ,  G11C7/14 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  G11C11/413

    Abstract: PURPOSE: To prevent noise from generating from an output switching and not to produce an error in read data by providing a transition detection circuit and a dummy chain block. CONSTITUTION: A dummy chain block consists of a dummy DEC (D-DEC), a dummy memory matrix D-WL and a dummy sense amplifier D-SA circuit block. A transition detection circuit ATD detects signal transition from an input and a control circuit ADD-BUFF, generates its pulse and makes a dummy chain DWL which reproduces transmission delay of a signal that passes through a matrix WLi of a memory cell usable by means of a reset signal. Then, it transfers a generation pulse through the dummy chain DWL which is made to be usable, generates a 2nd pulse which can make an extract data output storage circuit OL usable and makes the dummy chain DWL which is made to be usable unusable.

    SENSE AMPLIFIER FOR PROGRAMMABLE MEMORY PROVIDED WITH EXCELLENT SIGNAL SOURCE
    17.
    发明专利
    SENSE AMPLIFIER FOR PROGRAMMABLE MEMORY PROVIDED WITH EXCELLENT SIGNAL SOURCE 失效

    公开(公告)号：JPH06282993A

    公开(公告)日：1994-10-07

    申请号：JP21857892

    申请日：1992-07-25

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  OLIVO MARCO

    IPC: G11C11/417 ,  G11C7/06 ,  G11C16/06 ,  G11C16/28 ,  G11C17/00

    Abstract: PURPOSE: To increase the level of differential output by functionally connecting the output nodes of two control circuits to the respective sources of respective transistors for differential amplification. CONSTITUTION: As p-channel transistors TLR and TLM, load elements are cross- coupled and constitutes an output latch circuit for storing the extraction information of representative signals existent across output nodes OUTR and OUTM of sense amplifier together with input transistors TDR and TDM of differential amplifier. A timing signal ϕEN is inputted to one of respective control circuits. The other input is coincident with input nodes INM and INR of sense differential amplifier between the transistors TLM and TLR and lines MBL and RBL. The circuit is completed by equalizing transistors functionally connected across an evaluation bit line TES and transistors TEC and TEL across output nodes CM and CR.

    INTERNAL TIMING METHOD TO REWRITABLE MEMORY AND CIRCUIT THEREOF
    20.
    发明专利
    INTERNAL TIMING METHOD TO REWRITABLE MEMORY AND CIRCUIT THEREOF 失效

    公开(公告)号：JPH0896569A

    公开(公告)日：1996-04-12

    申请号：JP5038495

    申请日：1995-02-16

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  OLIVO MARCO ,  GOLLA CARLA MARIA

    IPC: G11C17/00 ,  G11C7/00 ,  G11C7/22 ,  G11C16/02 ,  G11C16/32 ,  G11C16/06

    Abstract: PURPOSE: To obtain an internal timing method to a rewritable memory and a circuit thereof. CONSTITUTION: A circuit 1 generates slow or fast overall timing configuration and flexible timing enabling the two configuration of pre-charge and detection intervals by giving the levels of two short and long periods. For conduct the generation of the timing, variable asymmetric propagation lines 5, 37 consisting of a series of basic delay elements 6-8, 38, 40 bringing data to an enable or disenable state on the basis of logical signals TIMS, PCS, and DETS stored are contained in the circuit 1, and the state is determined when a memory 100 executed by the circuit is debugged.

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