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    11.
    发明专利
    未知

    公开(公告)号：DE60127125D1

    公开(公告)日：2007-04-19

    申请号：DE60127125

    申请日：2001-09-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ROLANDI PAOLO

    IPC: G11C11/56 ,  G11C16/02 ,  G11C19/28

    Abstract: According to the multilevel programming method, each memory location (10a, 10b) can be programmed at a non-binary number of levels. An integer number of bits, for example 5, is stored in two adjacent memory locations (10a, 10b). To this end, the bits to be stored in the two locations are divided into two sets, wherein the first set defines a binary number of levels higher than the non-binary number of levels. During programming, if the first set of bits to be written corresponds to a number smaller than the non-binary number of levels, the first set of bits is written in the first location and the second set of bits is written in the second location (33, 34); if, instead, it is greater than the non-binary number of levels, the first set of bits is written in the second location and the second set of bits is written in the first location (35, 36). The bits of the first set written in the second location (10b) are stored in different levels with respect to the bits of the second set. Consequently, during reading, first it is verified(42) whether the levels reserved to the first set have been written, and the bits read in the two locations are appropriately associated to the two sets of bits.

    13.
    发明专利
    未知

    公开(公告)号：DE60025697D1

    公开(公告)日：2006-04-13

    申请号：DE60025697

    申请日：2000-02-08

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ROLANDI PAOLO ,  MONTANARO MASSIMO ,  ODDONE GIORGIO

    IPC: H02M3/07

    Abstract: A voltage boosting device for speeding power-up of multilevel nonvolatile memories, including a voltage regulator (11) and a charge pump (13) and having an output terminal (10); the voltage regulator (11) having a regulation terminal connected to the output terminal (10), and an output (16) supplying a control voltage (VL); the read charge pump (13) having an output connected to the output terminal (10) and supplying a read voltage (VR). The device further includes an enable circuit (12) connected to the output (16) and having a pump enable output (17) connected to a charge pump enable terminal (13) and supplying a pump enable signal (PE). The pump enable signal (PE) is set at a first logic level so as to activate the charge pump (13) when the read voltage (VR) is lower than a nominal value. In addition, the device generates a power-up sync signal (ATDS) which activates a read operation when the read voltage (VR) reaches its nominal value and a chip enable signal (CE) is set at an active value.

    14.
    发明专利
    未知

    公开(公告)号：DE69531823D1

    公开(公告)日：2003-10-30

    申请号：DE69531823

    申请日：1995-07-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  ROLANDI PAOLO ,  BARCELLA ANTONIO ,  FONTANA MARCO

    IPC: G06F11/20 ,  G11C7/20 ,  H03K3/356 ,  G11C16/06

    Abstract: A latch circuit (1) that is intentionally imbalanced, so that a first output (6) reaches ground voltage and a second output (7) reaches a supply voltage; and a fully static low-consumption fuse circuit the particularity whereof resides in that it comprises the intentionally unbalanced latch circuit (1) and a reversing branch that comprises the fuse to be programmed (6) and is adapted to reverse the operation of the latch circuit, so that in the virgin state the fuse (9) connects the second output (7) of the latch circuit (1) to the ground voltage and connects the first output (6) to the supply voltage.

    19.
    发明专利
    未知

    公开(公告)号：DE69611463T2

    公开(公告)日：2001-05-03

    申请号：DE69611463

    申请日：1996-10-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ROLANDI PAOLO

    IPC: G11C16/02 ,  G11C11/56

    Abstract: PCT No. PCT/IT96/00199 Sec. 371 Date Jun. 7, 1999 Sec. 102(e) Date Jun. 7, 1999 PCT Filed Oct. 30, 1996 PCT Pub. No. WO97/49088 PCT Pub. Date Dec. 24, 1997A multi-level memory circuit for binary information includes a plurality of memory cells each adapted to store more than one item of binary information, and each memory cell includes at least one floating gate MOS transistor. The information stored therein corresponds to the level of the cell threshold voltage. A write signal generating circuit is adapted to an input supply voltage and provides a write voltage to the memory cells. The write signal generating circuit generates internally at least one write voltage having a selectable or selected value from a number of discrete regulated values corresponding to the number of the discrete levels provided.

    20.
    发明专利
    未知

    公开(公告)号：DE69611463D1

    公开(公告)日：2001-02-08

    申请号：DE69611463

    申请日：1996-10-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ROLANDI PAOLO

    IPC: G11C16/02 ,  G11C11/56

    Abstract: PCT No. PCT/IT96/00199 Sec. 371 Date Jun. 7, 1999 Sec. 102(e) Date Jun. 7, 1999 PCT Filed Oct. 30, 1996 PCT Pub. No. WO97/49088 PCT Pub. Date Dec. 24, 1997A multi-level memory circuit for binary information includes a plurality of memory cells each adapted to store more than one item of binary information, and each memory cell includes at least one floating gate MOS transistor. The information stored therein corresponds to the level of the cell threshold voltage. A write signal generating circuit is adapted to an input supply voltage and provides a write voltage to the memory cells. The write signal generating circuit generates internally at least one write voltage having a selectable or selected value from a number of discrete regulated values corresponding to the number of the discrete levels provided.

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