-
公开(公告)号:DE69529908T2
公开(公告)日:2003-12-04
申请号:DE69529908
申请日:1995-11-30
Applicant: ST MICROELECTRONICS SRL
Inventor: TOMASINI LUCIANO , CASTELLO RINALDO , CLERICI GIANCARLO , BIETTI IVAN
Abstract: An operational amplifier frequency self-compensated with respect to closed-loop gain comprises a transconductance input stage (2) and an amplifier output stage (3) connected serially together to receive an input signal (Sin) on at least one input terminal (IN) of the amplifier and generate an amplified signal (Sout) on an output terminal (OUT) of the amplifier. Provided between the input (2) and output (3) stages is an intermediate node (S) which is connected to a compensation block (11) to receive a frequency-variable compensation signal (Sc) therefrom. According to the invention, the compensation block (11) is coupled with its input to the input terminal (IN) of the amplifier. The compensation block (11) is connected to receive at least the feedback signal (Sf). Preferably, the compensation signal (Sc) is variable as a function of a gain value (Gcl) which is determined by the feedback circuit, and said variation of the compensation signal occurs in a relationship of inverse proportionality to the gain value. This invention is useful in discrete circuits whose operational amplifier forms a device by itself, as well as in fully integrated circuits.
-
公开(公告)号:DE69529401D1
公开(公告)日:2003-02-20
申请号:DE69529401
申请日:1995-05-22
Applicant: ST MICROELECTRONICS SRL
Inventor: TOMASINI LUCIANO , CASTELLO RINALDO , BIETTI IVAN , CLERICI GIANCARLO
-
公开(公告)号:DE69228807T2
公开(公告)日:1999-08-12
申请号:DE69228807
申请日:1992-07-22
Applicant: ST MICROELECTRONICS SRL
Inventor: TOMASINI LUCIANO , CASTELLO RINALDO , ERRATICO PIETRO
Abstract: A circuit (1) for synthesizing an impedance associated with a telephone subscriber's circuit (2) connected to a two-wire telephone line (3) is a positive feedback configuration comprising: a single precision resistance (R) connected serially to the line (3); at least one low-pass filter; and an amplifier (7) between the filter (8) and the resistance (R). This circuit (1) allows both the termination impedance and the balance impedance to be synthesized through a single external precision component.
-
公开(公告)号:DE69224467D1
公开(公告)日:1998-03-26
申请号:DE69224467
申请日:1992-09-15
Applicant: ST MICROELECTRONICS SRL
Inventor: TOMASINI LUCIANO , CASTELLO RINALDO
IPC: H04M20060101 , H04M1/00 , H04M1/60 , H04M1/76 , H04M19/08
Abstract: A circuit is described which comprises an operational amplifier A, two resistors R1, R2, connected between the telephone line L and the inputs of the amplifier, a capacitor C, which is charged by a first bipolar transistor P1 controlled by the amplifier via a first FET transistor M1, a second bipolar transistor P2 arranged in parallel with the connection of the first transistor P1 and the capacitor C, a second FET transistor M2, equal to the first and with "source" and "gate" terminals connected to the corresponding terminals of the first one, and two current generators CC1, CC2, connected to the "drain" terminals, respectively, of the first and the second FET transistor and to the bases, respectively, of the first and the second bipolar transistor P1, P2. The currents I1, I2 of the two generators and the other parameters of the circuit are such as to keep the first and the second bipolar transistor respectively conducting and inhibited, except in the case when the line voltage drops below a minimum predetermined value: in such case, the first and the second transistor respectively switch to inhibition and conduction. The circuit has a lower "voltage loss" than the known circuits.
-
公开(公告)号:DE69223318D1
公开(公告)日:1998-01-08
申请号:DE69223318
申请日:1992-07-29
Applicant: ST MICROELECTRONICS SRL
Inventor: TOMASINI LUCIANO , CASTELLO RINALDO
-
公开(公告)号:DE60025584D1
公开(公告)日:2006-04-06
申请号:DE60025584
申请日:2000-05-12
Applicant: ST MICROELECTRONICS SRL
Inventor: GUINEA JESUS , TOMASINI LUCIANO , MILANESE CARLO MARIA
Abstract: The present invention refers to a method and to an equalizer circuit of signals transmitted on a line. In an embodiment the equaliser circuit of signals transmitted on a line having an attenuation comprising: an analogical adaptive filter (1) applied in series to said line comprises at least two transconductance filters having a bias current (Pc1-Pcn) each and to which it is associated at least one pole and at least one zero the position in frequency of which in the working band (B) is variable in response to said bias current (Pc1-Pcn); a retroaction circuit (3, 4, 5, 6, 7) applied to the output of said filter (1) able to vary said bias current (Pc1-Pcn); said bias current (Pc1-Pcn) varies at the varying of said attenuation of said line; characterised in that said at least two transconductance filters have said bias current of prefixed value; said bias current is made to vary at the increasing of said attenuation so that said at least one pole is moved toward the high frequencies; said bias current is made to vary at the increasing of said attenuation so that said at least a zero is moved toward the low frequencies.
-
公开(公告)号:ITVA20020050A1
公开(公告)日:2004-04-05
申请号:ITVA20020050
申请日:2002-10-04
Applicant: ST MICROELECTRONICS SRL
Inventor: CATTANEO CLAUDIO , DE LAURENTIIS PIERPAOLO , TOMASINI LUCIANO
IPC: H03B20060101 , H03G1/00 , H03K5/24 , H04L25/02
-
公开(公告)号:DE69530773D1
公开(公告)日:2003-06-18
申请号:DE69530773
申请日:1995-10-30
Applicant: ST MICROELECTRONICS SRL
Inventor: TOMASINI LUCIANO , CASTELLO RINALDO , CLERICI GIANCARLO , BIETTI IVAN
IPC: H03K17/06
Abstract: The interface circuit described is disposed between a generator (LG) of control signals (CS) and a plurality of electronic switches (SW) in order to produce boosted voltage signals (SCS) corresponding to the control signals (CS) for activating the electronic switches (SW). To avoid the use of capacitors with high capacitance and thus to save area of the integrated circuit, the circuit comprises a generator (SCK) of boosted-voltage clock signals ( phi , phi ) and a plurality of voltage multipliers (VM) each having an input connected to an output of the control signal generator (LG), an output connected to at least one terminal for activating an electronic switch (SW) and two control terminals connected to the boosted-voltage clock-signal generator.
-
公开(公告)号:DE69529908D1
公开(公告)日:2003-04-17
申请号:DE69529908
申请日:1995-11-30
Applicant: ST MICROELECTRONICS SRL
Inventor: TOMASINI LUCIANO , CASTELLO RINALDO , CLERICI GIANCARLO , BIETTI IVAN
Abstract: An operational amplifier frequency self-compensated with respect to closed-loop gain comprises a transconductance input stage (2) and an amplifier output stage (3) connected serially together to receive an input signal (Sin) on at least one input terminal (IN) of the amplifier and generate an amplified signal (Sout) on an output terminal (OUT) of the amplifier. Provided between the input (2) and output (3) stages is an intermediate node (S) which is connected to a compensation block (11) to receive a frequency-variable compensation signal (Sc) therefrom. According to the invention, the compensation block (11) is coupled with its input to the input terminal (IN) of the amplifier. The compensation block (11) is connected to receive at least the feedback signal (Sf). Preferably, the compensation signal (Sc) is variable as a function of a gain value (Gcl) which is determined by the feedback circuit, and said variation of the compensation signal occurs in a relationship of inverse proportionality to the gain value. This invention is useful in discrete circuits whose operational amplifier forms a device by itself, as well as in fully integrated circuits.
-
公开(公告)号:DE69228812T2
公开(公告)日:1999-08-12
申请号:DE69228812
申请日:1992-09-14
Applicant: ST MICROELECTRONICS SRL
Inventor: TOMASINI LUCIANO , CASTELLO RINALDO
Abstract: The invention relates to a method for implementing an impedance associated with a monolithically integrated telephone subscriber circuit (2) which is connected to a telephone line (3) having at least one terminal pair (L+,L-). The method consists of providing, a single resistor (Re) connected serially to one terminal (L+) of the telephone line (3), and circuit means (1) connected in a closed loop to the terminal (L+) to divide, by a predetermined factor, the value of the resistor (Re) on the occurrence of DC or very low frequency signals.
-
-
-
-
-
-
-
-
-