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    13.
    发明专利
    未知

    公开(公告)号：DE69826471D1

    公开(公告)日：2004-10-28

    申请号：DE69826471

    申请日：1998-10-15

    Applicant: ST MICROELECTRONICS SRL

    Inventor： DALLA LIBERA GIOVANNA ,  VAJANA BRUNO

    IPC: H01L21/8247 ,  H01L27/115

    Abstract: The invention relates to a simplified DPCC process for making non-self-aligned floating gate semiconductor memory cells of the FLOTOX EEPROM type as incorporated to a cell matrix having control circuitry associated therewith, wherein each cell has a selection transistor associated therewith, the process comprising at least the following steps: growing or depositing a gate dielectric layer of the selection transistor and the cell; tunnel masking to define the tunnel area with a dedicated etching step for cleaning the semiconductor surface; growing the tunnel oxide; depositing and doping the first polysilicon layer poly1. The process further comprises the following steps: poly1 masking to fully define the floating gate of the cell, the poly1 being removed from the area of the selection transistor during this step; depositing or growing the interpoly dielectric and forming tunnel oxide and interpoly dielectric; depositing or growing the interpoly dielectric and forming the overall gate dielectric of the selection transistor, which will therefore consist of the stacked interpoly dielectric and gate dielectric as previously grown or deposited; matrix masking to only remove interpoly dielectric from the circuitry; depositing and doping a second polysilicon layer poly2; masking the second later of polysilicon to define the control and selection gate; poly etching in the matrix as far down as the intermediate dielectric layer; poly etching in the circuitry the whole short-circuited poly1/poly2 stack.

    14.
    发明专利
    未知

    公开(公告)号：IT1303282B1

    公开(公告)日：2000-11-06

    申请号：ITMI982334

    申请日：1998-10-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CREMONESI CARLO ,  VAJANA BRUNO ,  BOTTINI ROBERTA ,  DALLA LIBERA GIOVANNA

    IPC: H01L21/265 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115

    Abstract: A process formes a structure incorporating at least one circuitry transistor and at least one non-volatile memory cell of the EEPROM type with two self-aligned polysilicon levels having a storage transistor and an associated selection transistor in a substrate of semiconductor material including field oxide regions bounding active area regions. The process comprises the steps of in the active area regions, forming a gate oxide layer and defining a tunnel oxide region included in the gate oxide layer depositing and partly defining a first polysilicon layer forming an interpoly dielectric layer and removing the interpoly dielectric layer at least at the circuitry transistor depositing a second polysilicon layer selectively etching away the second polysilicon layer at the cell, and the first and second polysilicon layers at the circuitry transistor and selectively etching away the interpoly dielectric layer and the first polysilicon layer at the cell. After forming and before partially defining the first polysilicon layer, the process implants at least at the channel region of the floating-gate storage transistor for adjusting the transistor threshold.

    15.
    发明专利
    未知

    公开(公告)号：IT1302282B1

    公开(公告)日：2000-09-05

    申请号：ITMI982082

    申请日：1998-09-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CREMONESI CARLO ,  VAJANA BRUNO ,  BOTTINI ROBERTA ,  DALLA LIBERA GIOVANNA

    IPC: H01L21/8247 ,  H01L27/115

    Abstract: Process for manufacturing of an integrated structure including at least one circuitry transistor and at least one non-volatile EEPROM memory cell with relative selection transistor, including at least a first stage of growth and definition of a gate oxide layer on a silicon substrate, a second stage of definition of a tunnel oxide region in said gate oxide layer, a third stage of deposition and definition of a first polysilicon layer on said gate oxide layer and on said tunnel oxide region, a fourth stage of growth and definition of an intermediate dielectric layer on said first polysilicon layer, a fifth stage of selective etching and removal of said dielectric intermediate layer in a region for said circuitry transistor, a sixth stage of ionic implantation of a dopant with a first type of conductivity in order to introduce said dopant into a channel region for said circuitry transistor in order to adjust its threshold voltage, a seventh stage of deposition and definition of a second polysilicon layer on said integrated structure, an eighth stage of selective etching and removal of said second polysilicon layer in a region for said memory cell, and of said first and second polysilicon layers in said region for said circuitry transistor in order to form said circuitry transistor, and a ninth stage of selective etching and removal of said intermediate dielectric layer and of said first polysilicon layer in said region for said memory cell, wherein during said fifth stage said intermediate dielectric layer is etched and removed also in a region that is destined to form a channel of said selection transistor, and said sixth stage of ionic implantation therefore allows to introduce said dopant into said channel region and therefore to increase the threshold voltage of said selection transistor.

    18.
    发明专利
    未知

    公开(公告)号：DE69833247D1

    公开(公告)日：2006-04-06

    申请号：DE69833247

    申请日：1998-10-02

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PATELMO MATTEO ,  DALLA LIBERA GIOVANNA ,  GALBIATI NADIA ,  VAJANA BRUNO

    IPC: H01L21/8246 ,  H01L21/8247 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/105 ,  H01L27/112 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    Abstract: The invention relates to a method of producing a multi-level memory of the ROM type in a CMOS process of the dual gate type, which method comprises at least the following steps: on a semiconductor substrate, defining respective active areas for transistors of ROM cells (1), electrically erasable non-volatile memory cells, and low- and high-voltage transistors; depositing a layer of gate oxide over said active areas; depositing a polysilicon layer over the gate oxide layer; masking, and then etching, the polysilicon layer to define, by successive steps, respective gate regions of the ROM cells, non-volatile cells, and low- and high-voltage transistors; characterized in that it further comprises the following steps: masking the polysilicon layer (4) of some of the transistors of the ROM cells (1), and implanting a first dopant species (N) in the active areas (2) of the exposed transistors; removing the mask from the polysilicon layer (4), and implanting a second dopant species (P) in said previously covered layer; masking and subsequently etching the polysilicon layer to define the gate regions of the ROM cell transistors.

    19.
    发明专利
    未知

    公开(公告)号：DE69431598D1

    公开(公告)日：2002-11-28

    申请号：DE69431598

    申请日：1994-11-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PIO FREDERICO ,  VAJANA BRUNO ,  PARUZZI PAOLA

    IPC: G11C17/00 ,  G05F3/24 ,  G11C5/14 ,  G11C11/56 ,  G11C16/06

    Abstract: The present invention relates to a monolithically integrable predetermined voltage generator (1) comprising a node (IN) held at a constant voltage (Vpp) and a plurality of circuit branches (2a, 2b, 2c and 2d) each of which incorporates at least one turn on control terminal (3a, 3b, 3c and 3d) and which are interconnected in such a manner that at least one of them leads to said node (IN). Across each of the branches (2a, 2b, 2c and 2d) a corresponding voltage drop is present when the branch is turned on and obtained from a certain number of active elements included in the branch. In accordance with a preferred embodiment, diode-connected MOS transistors are used as active elements. The generator also comprises an output terminal (OUT) associated with at least one of said branches at which is generated a predetermined voltage value. A control signal is applied to at least one turn on control terminal (3a, 3b, 3c and 3d) of said plurality of branches for turning on a predetermined subset of said plurality of branches and generating at the output terminal (OUT) a voltage lower than that at said node (IN). Each of the predetermined voltage values is a predetermined combination of the voltage drops on the turned on branches. In a preferred application, the generator of the present invention is used in a multilevel EEPROM memory circuit for generating a plurality of programming voltages for the memory cells.

    20.
    发明专利
    未知

    公开(公告)号：IT1311325B1

    公开(公告)日：2002-03-12

    申请号：ITTO991112

    申请日：1999-12-17

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PATELMO MATTEO ,  DALLA LIBERA GIOVANNA ,  VAJANA BRUNO

    IPC: H01L29/78

    Abstract: A transistor of the integrated MOS type with a high threshold voltage and low multiplication coefficient is formed in a chip that includes a substrate and defining an active area delimited by field oxide regions. The active area partially houses a tub having the same type of conductivity as the substrate and a greater doping level. In particular, the tub occupies a first half of the active area, while a second half of the active area is formed directly by the substrate. A gate region is present above the substrate and is isolated from the substrate by means of a gate oxide layer. The gate region is arranged partially above the second half of the active area and partially above the tub. The transistor also comprises a source region, which is formed in the tub on a first side of the gate region, and a drain region, which is arranged in the second half of the active area, on a second side of the gate region. Therefore, the transistor has a channel region which is delimited between the source region and drain region and one half of which has a first doping level and the other half a second doping level greater than the first doping level; consequently, the transistor has a high threshold voltage.

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