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    RLL/NRZ DECODER PROGRAMMABLE FOR SINGLE/DUAL-BIT OUTPUT DATASTREAM
    11.
    发明专利
    RLL/NRZ DECODER PROGRAMMABLE FOR SINGLE/DUAL-BIT OUTPUT DATASTREAM 失效

    公开(公告)号：JPH07182791A

    公开(公告)日：1995-07-21

    申请号：JP30156994

    申请日：1994-11-10

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MOLONEY DAVID ,  GADDUCCI PAOLO ,  DEMICHELI MARCO ,  ALINI ROBERTO

    IPC: G06F3/06 ,  G11B20/10 ,  G11B20/14 ,  H03M5/14

    Abstract: PURPOSE: To facilitate the decoder of an operation mode by programming one of the output stream of the single bit of decoded data and the dual bit output stream of the decoded data. CONSTITUTION: The second re-timed output signals of a flip-flop B are supplied to the other input 1 of a MUX OUT multiplexer and the input of a forth flip- flop BB and the signals are sampled as the flip-flop AA by a second fractional clock frequency VCO/3. In this case, by performing different selection between the two inputs of an output multiplexers and selecting the one input, a single bit decoding NRZ stream becomes utilizable in the output of this decoder.

    14.
    发明专利
    未知

    公开(公告)号：DE69327053D1

    公开(公告)日：1999-12-23

    申请号：DE69327053

    申请日：1993-09-21

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MOLONEY DAVID ,  GADDUCCI PAOLO ,  BETTI GIORGIO ,  ALINI ROBERTO

    IPC: G11B20/10 ,  G11B20/14 ,  H03M5/06 ,  H03M5/14

    Abstract: In a decoder for decoding a serial data stream, employing an extracted base clock signal, synchronous with an input, coded, serial data stream, a fractionary frequency clock signal for sampling a decoded output data stream and a second fractionary clock signal for synthesizing a pre-decoded value produced by a first combinative logic network within a second combinative logic network to produce a decoded value that is sent to an output sampling flip-flop, a pipelined operation is implemented by momentarily storing the bits that are processed in the second combinative logic network and by anticipating of two full cycles of the synchronous base clock the processing by said first combinative network of the n-number of bits handled by the decoder. Each one of the two combinative logic networks is permitted to complete its decoding process within a full clock cycle in advance of the raising front of the outpunt sampling clock signal. With the same fabrication technology and therefore with the same propagation delay of the two combinative logic networks, the maximum operating spead may be doubled. A limited number of additional components are required to implement the pipelined operation of the invention.

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