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公开(公告)号：DE69514090T2
公开(公告)日：2000-05-25
申请号：DE69514090
申请日：1995-03-31
Applicant: ST MICROELECTRONICS SRL , CONS RIC MICROELETTRONICA
Inventor： PULVIRENTI FRANCESCO , URSINO RICCARDO , GARIBOLDI ROBERTO
IPC: H03F3/45 , H03K3/011 , H03K3/0231 , H03K3/354 , H03K4/06 , H03K19/0948
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公开(公告)号：DE69408665T2
公开(公告)日：1998-10-15
申请号：DE69408665
申请日：1994-08-12
Applicant: CONS RIC MICROELETTRONICA , ST MICROELECTRONICS SRL
Inventor： PULVIRENTI FRANCESCO , GARIBOLDI ROBERTO
IPC: H02M3/07
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公开(公告)号：DE69533308D1
公开(公告)日：2004-09-02
申请号：DE69533308
申请日：1995-05-16
Applicant: ST MICROELECTRONICS SRL , CONS RIC MICROELETTRONICA
Inventor： PULVIRENTI FRANCESCO , GARIBOLDI ROBERTO
IPC: G01R19/165 , G01R31/02 , G05B19/042 , G05B19/05
Abstract: The invention relates to a method for detecting an open load by means of a driver having at least one main power transistor (M10) connected to the load (L) and one auxiliary transistor (M11) connected in parallel with the main transistor (M10) between a first power supply voltage reference (Vs) and a second voltage reference (GND), the method providing a comparison between a first voltage (VIN1) present on a terminal (S10) connected to the load of the main transistor (M10) and a second voltage (VIN2) present on a terminal (S11) of the auxiliary transistor (M11). The invention also relates to a circuit for detecting an open load (L), in which the said method is implemented.
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公开(公告)号：DE69623754T2
公开(公告)日：2003-05-08
申请号：DE69623754
申请日：1996-05-31
Applicant: ST MICROELECTRONICS SRL , CONS RIC MICROELETTRONICA
Inventor： URSINO RICCARDO , GARIBOLDI ROBERTO
Abstract: The invention relates to a voltage regulator connected between first (VS) and second (GND) voltage references and having an output terminal (O1) for delivering a regulated output voltage (Vout), which voltage regulator comprises at least one voltage divider (11), connected between the output terminal (O1) and the second voltage reference (GND), and a serial output element (18) connected between the output terminal (O1) and the first voltage reference (VS), the voltage divider (11) being connected to the serial output element (18) by a first conduction path which includes at least one error amplifier (EA) of the regulated output voltage (Vout) whose output is connected to at least one driver (DR) for turning off the serial output element (18), the voltage regulator comprising, between the voltage divider (11) and the serial output element (18), at least a second conduction path for turning off the serial output element (18) according to the value of the regulated output voltage (Vout), in advance of the action of the first conduction path. The invention also concerns a method of turning off a serial output element (18) as a regulated output voltage (Vout) from a voltage regulator (10) changes.
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公开(公告)号：DE69421083D1
公开(公告)日：1999-11-11
申请号：DE69421083
申请日：1994-11-17
Applicant: ST MICROELECTRONICS SRL , CONS RIC MICROELETTRONICA
Inventor： COLLETTI PAOLO , BONTEMPO GREGORIO , PULVIRENTI FRANCESCO , GARIBOLDI ROBERTO
Abstract: The purpose of the present invention is to supply a method and a circuit simple and accurate enough to protect at least one transistor against exceeding a complex limit implying processing of multiple electrical quantities associated with said transistor. Since in many practical cases said complex limit corresponds to the product of at least two quantities, typically a current and a voltage, the circuit in accordance with the present invention generates electrical signals basically proportional to said quantities, multiplies them, compares the product with a reference signal corresponding to the limit placed on the transistor and acts on the transistor in such a way that said limit is not exceeded. Advantageously the multiplication of currents can be provided simply by means of connection in series of bipolar transistor junctions at which said currents are supplied to the respective emitters. In this case it is additionally advantageous to generate the reference signal by means of connection in series of the bipolar transistor junctions in such a manner as to have an analogous behaviour of the multiplier and the generator.
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Patent Agency Ranking
公开(公告)号：JPH1168530A
公开(公告)日：1999-03-09
申请号：JP17706298
申请日：1998-06-24
Applicant: ST MICROELECTRONICS SRL
Inventor： GENOVA ANGELO , TARANTOLA MARIO , CANTONE GIUSEPPE , GARIBOLDI ROBERTO
IPC: H03K17/06
Abstract: PROBLEM TO BE SOLVED: To provide a circuit, capable of more efficiently charging a capacitance without increasing the power consumption for a parasitic transistor. SOLUTION: A circuit that charges a capacitance C with an LDMOS-LD integrated transistor is provided with a switching means SWb controlled by a logical signal UVLO. Hereby, the switching means SWb is made into active state, in order to charge a board node with the current whose maximum value is restricted to the pre-established value during a phase, in which a supply voltage Vs of an integrated circuit is lower than the minimum switch-on voltage of the same integrated circuit.
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公开(公告)号：JPH11168369A
公开(公告)日：1999-06-22
申请号：JP19477998
申请日：1998-07-09
Applicant: ST MICROELECTRONICS SRL
Inventor： GENOVA ANGELO , CANTONE GIUSEPPE , GARIBOLDI ROBERTO
Abstract: PROBLEM TO BE SOLVED: To provide an inexpensive integrated device of relatively simple and compact constitution without receiving interference at the time of switching. SOLUTION: In this integrated device 105 for a switching system provided with a control means 110 for generating switching control signals, a reference means 120 for generating a reference amount Qref and a means 110 for using the reference amount, the means 130 for storing the reference amount, a switch means 122 for connecting the reference means 120 to a using means 110 and a storage means 130 so as to supply the reference amount Qref in a first operation state and interrupting the reference means 120 from the using means 110, connecting the storage means 130 to the using means 110 and supplying the stored reference amount Qref in a second operation state and a filter means 135 for maintaining the switch means 122 in the second operation sate during a filtering period corresponding to the switching of control signals Sh are provided.
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公开(公告)号：JPH1168531A
公开(公告)日：1999-03-09
申请号：JP17718598
申请日：1998-06-24
Applicant: ST MICROELECTRONICS SRL
Inventor： TARANTOLA MARIO , CANTONE GIUSEPPE , GENOVA ANGELO , GARIBOLDI ROBERTO
IPC: H03K17/06 , H03K17/0812 , H03K17/16
Abstract: PROBLEM TO BE SOLVED: To surely control a gate voltage so that an LDMOS transistor can not be switched on undesiredly by providing a 2nd inverter provided with an input end, to which a 2nd logical signal is inputted and an output end which is connected to a gate node of the LDMOS transistor. SOLUTION: In a pMOS transistor M1, its source is connected to the cathode of a diode D1 and to a charging terminal of a bootstrap capacitor Cp, also its drain is connected to the drain of an nMOS transistor M2 and to the gate of an LDMOS integrated transistor LD. The source of the transistor M2 is connected to an output node A of a control inverter 101 and to the other terminal of the condenser Cp. Then gates of the transistors M1 and M2 are controlled by a logical signal UVLOb and prevent the transistor LD from being turned on accidentally.
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公开(公告)号：DE69421075T2
公开(公告)日：2000-03-02
申请号：DE69421075
申请日：1994-06-10
Applicant: CONS RIC MICROELETTRONICA
Inventor： BONTEMPO GREGORIO , PULVIRENTI FRANCESCO , COLLETTI PAOLO , GARIBOLDI ROBERTO
IPC: H02H3/08 , H03K17/082 , H03K17/284
Abstract: The invention relates to a non-dissipative device for protecting against overloading an integrated circuit having multiple independent channels, being of the type which comprises an input terminal (IN) and an output terminal (OUT) having an integrated switch (1) connected therebetween which consists of a first or input portion (2), a logic gate (PL1) with two inputs (I3,I4) a second or control portion (3), and a third or output portion (4), all in series with one another. The device further comprises a circuit (A) for generating the on- and off-times (Ton,Toff) of the integrated switch (1) connected between an output (O4) of the third portion (4) and an input terminal (I4) of said logic gate (PL1).
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公开(公告)号：JPH1174769A
公开(公告)日：1999-03-16
申请号：JP17734198
申请日：1998-06-24
Applicant: ST MICROELECTRONICS SRL
Inventor： TARANTOLA MARIO , CANTONE GIUSEPPE , GENOVA ANGELO , GARIBOLDI ROBERTO
Abstract: PROBLEM TO BE SOLVED: To automatically switch off an LDMOS transistor by having a zener diode which is biased forward between a supply node and a source node of an LDMOS transistor and providing a 2nd zener diode in place of a charging diode. SOLUTION: A 1st Zener diode Z1 is used in place of a charging diode of a capacity Cp which exists at Vs supply voltage. A 2nd Zener diode Z2 is connected between a source node S of a transistor LD and the supply node Vs. When Zehner voltages VZ1 and VZ2 of the diodes Z1 and Z2 satisfy the condition Vs>VZ1, there holds VTH>VZ1-VZ2, and when Vs Vs+ Vbe-VZ2 holds. VTH is the threshold voltage of the transistor LD, and the difference between the source voltage of the transistor LD and the substrate voltage is equal to VZ2-nVbe.
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