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    Single supply voltage, nonvolatile memory device with cascoded column decoding
    11.
    发明公开
    Single supply voltage, nonvolatile memory device with cascoded column decoding 审中-公开
    NichtflüchtigeSpeicheranordnung mit einziger Speisespannung mit Kaskode-Spaltendekodiererung

    公开(公告)号：EP1324345A1

    公开(公告)日：2003-07-02

    申请号：EP01830808.0

    申请日：2001-12-27

    Applicant: STMicroelectronics S.r.l.

    Inventor： Khouri, Osama ,  Bedeschi, Ferdinando

    IPC: G11C16/24

    CPC classification number: G11C13/0026 ,  G11C7/22 ,  G11C13/0038 ,  G11C16/24 ,  G11C2216/22

    Abstract: A nonvolatile memory device (1') is described comprising a memory array (2), a row decoder (3) and a column decoder (4) for addressing the memory cells (7) of the memory array (2), and a biasing stage (13,19) for biasing the drain terminal of the addressed memory cell (7). The biasing stage (13,19) is coupled between the column decoder (4) and the memory array (2) and comprises a biasing transistor (13) having a drain terminal connected to the column decoder (4), a source terminal connected to the drain terminal of the addressed memory cell (7), and a gate terminal receiving a driving signal of a logic type, the logic levels whereof are defined by precise and stable voltages and are generated by a first driving circuit (19) formed by a driving stage (20) and a buffer (21), cascade-connected.

    Abstract translation: 描述了一种非易失性存储器件（1'），其包括用于寻址存储器阵列（2）的存储器单元（7）的存储器阵列（2），行解码器（3）和列解码器（4） （13,19），用于偏置寻址的存储单元（7）的漏极端子。 偏置级（13,19）耦合在列解码器（4）和存储器阵列（2）之间，并且包括偏置晶体管（13），其漏极端子连接到列解码器（4），源极端子连接到 所述寻址的存储单元（7）的漏极端子和接收逻辑类型的驱动信号的栅极端子，其逻辑电平由精确和稳定的电压限定，并由由第一驱动电路（19）形成的第一驱动电路 驱动级（20）和缓冲器（21），级联。

    Method and device for irreversibly programming and reading nonvolatile memory cells
    12.
    发明公开
    Method and device for irreversibly programming and reading nonvolatile memory cells 审中-公开
    方法和装置用于非易失性存储器单元的不可逆编程和读取

    公开(公告)号：EP2045814A1

    公开(公告)日：2009-04-08

    申请号：EP07425616.5

    申请日：2007-10-03

    Applicant: STMicroelectronics S.r.l.

    Inventor： Resta, Claudio ,  Bedeschi, Ferdinando ,  Pellizzer, Fabio

    IPC: G11C16/02 ,  G11C16/10 ,  G11C17/14 ,  G11C16/26

    CPC classification number: G11C13/0069 ,  G11C11/005 ,  G11C11/5678 ,  G11C13/0004 ,  G11C17/16 ,  G11C17/165 ,  G11C2013/0078

    Abstract: In a nonvolatile memory device, data stored in a memory cell (21a, 21b) are associated to whether or not the memory cell is switchable between a first state and a second state. Memory cells are irreversibly programmed by applying an irreversible programming signal (I IRP ), such that the nonvolatile memory cells (21a) are made not switchable between the first state and the second state in response to the irreversible programming signal (I IRP ). Reading memory cells includes: assessing (100, 110, 120, 140, 150, 160) whether a memory cell (21a, 21b) is switchable between a first state and a second state; determining that a first irreversible logic value ("1") is associated to the memory cell (21a), if the memory cell (21a) is not switchable between the first state and the second state (130); and determining that a second irreversible logic value ("0") is associated to the memory cell (21b), if the memory cell (21b) is switchable between the first state and the second state (170).

    Abstract translation: 在非易失性存储器装置中，存储在存储器单元中的数据（21A，21B）被关联到所述存储器单元是否为第一状态和第二状态之间切换。 存储单元通过施加不可逆编程信号（I IRP）不可逆编程，检查做了非易失性存储单元（21a）的由响应于不可逆编程信号（I IRP）的第一状态和所述第二状态之间不切换。 读取存储器单元包括：评估（100，110，120，140，150，160）是否存储单元（21A，21B）为第一状态和第二状态之间切换; 确定性挖掘做了第一不可逆逻辑值（“1”）关联到所述存储单元（21a），如果存储单元（21a）没有所述第一状态和所述第二状态（130）之间切换; 和确定性挖掘做了第二不可逆逻辑值（“0”）被关联到所述存储单元（21B），如果存储单元（21B）是在第一状态和第二状态（170）之间切换。

    Fast reading, low power consumption memory device and reading method thereof
    16.
    发明公开
    Fast reading, low power consumption memory device and reading method thereof 审中-公开
    存储器阵列具有快速读出操作和更低的功耗和相应的读出方法

    公开(公告)号：EP1548744A1

    公开(公告)日：2005-06-29

    申请号：EP03425820.2

    申请日：2003-12-23

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Resta, Claudio ,  Bedeschi, Ferdinando ,  Torelli, Guido

    IPC: G11C11/34 ,  G11C8/10

    CPC classification number: G11C13/0004 ,  G11C7/12 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004

    Abstract: A memory device includes a plurality of memory cells (3), arranged in row and columns, memory cells (3) arranged on the same column having respective first terminals (3a) connected to a same bit line (12) and memory cells (3) arranged on the same row having respective second terminals (3b) selectively connectable to a same word line (13); a supply line (9) providing a supply voltage (V A ); a column addressing circuit (4) for addressing a bit line (12) corresponding to a memory cell (3) to be read; and a row addressing circuit (5) for addressing a word line (13) corresponding to the memory cell (3) to be read. Moreover, the column addressing circuit (4) is configured to bias the addressed bit line (12) corresponding to the memory cell (3) to be read substantially at the supply voltage (V A ).

    Abstract translation: 一种存储器装置包括布置在具有连接到相同的位线（12）和存储单元respectivement第一端子（3a）中同一列的存储单元的多个（3），以行和列排列的存储器单元（3）（3 ）布置在具有respectivement第二端子在同一行（3B）选择性地连接到一个相同的字线（13）; 一电源线（9）提供电源电压（VA）; 用于寻址对应于存储单元（3）要被读出的位线（12）的柱寻址电路（4）; 和要被读取用于寻址对应于存储单元（3）的字线（13）的行寻址电路（5）。 更完了，列寻址电路（4）被配置成偏置相应于存储单元（3）被寻址的位线（12）被在电源电压（VA）基本上读取。

    Circuit and method for temperature tracing of devices including an element of chalcogenic material, in particular phase change memory devices
    17.
    发明公开
    Circuit and method for temperature tracing of devices including an element of chalcogenic material, in particular phase change memory devices 有权
    和用于chalcogenische元件，特别是相变存储器元件的Tempeaturüberwachung电路布置

    公开(公告)号：EP1420412A1

    公开(公告)日：2004-05-19

    申请号：EP02425706.5

    申请日：2002-11-18

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Khouri, Osama ,  Bedeschi, Ferdinando ,  Resta, Claudio

    IPC: G11C11/34

    CPC classification number: G11C7/04 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/009 ,  G11C2029/5002 ,  G11C2213/79

    Abstract: A phase change memory includes a temperature sensor having a resistance variable with temperature with the same law as a phase-change storage element. The temperature sensor is formed by a resistor (20) of chalcogenic material furnishing an electrical quantity (V(T), I(T)) that reproduces the relationship between the resistance of a phase change memory cell and temperature; the electrical quantity is processed (21) so as to generate reference quantities as necessary for writing and reading the memory cells. The chalcogenic resistor (20) has the same structure as a memory cell and is programmed with precision, preferably in the reset state.

    Abstract translation: 一种相变存储器包括：具有与具有相同法律作为一种相变存储元件温度的电阻变化的温度传感器。 温度传感器由电量的硫族化物材料的家具的电阻器（20）所形成（V（T），I（T））做再现相变存储单元和温度的电阻之间的关系; 电量进行处理（21），以便产生参考量所必需的写入和读出的存储器单元。 硫属化物的电阻（20）具有相同的结构的存储单元和被编程有精度，最好是在复位状态。

    Single supply voltage, nonvolatile phase change memory device with cascoded column selection and simultaneous word read/write operations
    18.
    发明公开
    Single supply voltage, nonvolatile phase change memory device with cascoded column selection and simultaneous word read/write operations 有权
    非易失性的相变存储器的单电源电压，共源共栅列选择和同时读取和写入操作Wortlese-

    公开(公告)号：EP1326258A2

    公开(公告)日：2003-07-09

    申请号：EP02028616.7

    申请日：2002-12-20

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Khouri, Osama ,  Bedeschi, Ferdinando

    IPC: G11C16/24

    CPC classification number: G11C11/5678 ,  G11C7/04 ,  G11C7/22 ,  G11C8/10 ,  G11C13/0004 ,  G11C13/0026 ,  G11C2216/22

    Abstract: A nonvolatile memory device (10'; 10") is described comprising a memory array (11), a row decoder (12) and a column selector (13) for addressing the memory cells (16) of the memory array (11), and a biasing stage (22; 36, 28) for biasing the array access device terminal of the addressed memory cell (16). The biasing stage (22; 36 28) is arranged between the column selector (13) and the memory array (11) and comprises a biasing transistor (22; 36) having a drain terminal connected to the column selector (13), a source terminal connected to the array access device terminal of the addressed memory cell (16), and a gate terminal receiving a logic driving signal, the logic levels of which are defined by precise and stable voltages and are generated by a logic block (31) and an output buffer (32) cascaded together. The output buffer (32) may be supplied with either a read voltage (VREAD) or a program voltage (VPROG) supplied by a multiplexer (33). The biasing transistor (22; 36) may be either included as part of the column selector (13) and formed by the selection transistor (22) which is closest to the addressed memory cell (16) or distinct from the selection transistors (20, 21, 22) of the column selector (13).

    Abstract translation: 一种非易失性存储器装置（10”，10“）被描述为包括用于寻址所述存储器阵列的所述存储器单元（16）的存储器阵列（11），行译码器（12）和列选择器（13）（11） 用于偏压被寻址的存储器单元的阵列接入设备终端（16）的偏置级（22; 36 28）;以及偏压级（36，28 22）。在所述列选择器（13）和存储器阵列（之间布置 11）和包括偏压晶体管（22; 36），具有连接到列选择器（13），连接到所述寻址的存储器单元（16）的阵列存取装置端子的源极端子的漏极端子和栅极端子接收 逻辑驱动信号时，逻辑电平在此通过精确且稳定的电压定义的和由一个逻辑块（31）产生并输出缓冲器（32）级联在一起，输出缓冲器（32）可以与任一个读取电压提供 （VREAD）或编程电压（VPROG）通过一个多路复用器（33）的偏置晶体管提供（22; 36）。可以是eithe ř包括作为列选择器（13）的一部分，并且由选择晶体管（22），所有这些是最近的到所寻址的存储器单元（16）或不同从列选择器的选择晶体管（20，21，22）而形成（13 ）。

    A semiconductor memory device with information loss self-detect capability
    20.
    发明公开
    A semiconductor memory device with information loss self-detect capability 有权
    Halbleiterspeicheranordnung mitFähigkeitzur Informationsverlusterkennung

    公开(公告)号：EP1717817A1

    公开(公告)日：2006-11-02

    申请号：EP05103557.4

    申请日：2005-04-29

    Applicant: STMicroelectronics S.r.l.

    Inventor： Resta, Claudio ,  Bedeschi, Ferdinando

    IPC: G11C16/34 ,  G11C16/02

    CPC classification number: G11C13/0004 ,  G11C11/22 ,  G11C11/2275 ,  G11C13/0033 ,  G11C13/0069 ,  G11C16/3431 ,  G11C2013/0083

    Abstract: A semiconductor memory device ( 100 ), including a plurality of programmable memory cells ( MC ) each one adapted to be brought into one among at least a first status and a second status, said plurality of memory cells including memory cells intended to store data, and means for accessing ( 115,130,135 ) the memory cells for reading/modifying their status. At least one memory cell ( FMC ) in said plurality is used as detector memory cell, and control means ( 145 ) operatively associated with the at least one detector memory cell are provided, said control means being adapted to establishing a potential loss of the data stored in the memory cells of said plurality based on a detected first status of the at least one detector memory cell.

    Abstract translation: 一种半导体存储器件（100），包括多个可编程存储器单元（MC），每个可编程存储器单元适于在至少第一状态和第二状态之间变成一个，所述多个存储器单元包括用于存储数据的存储器单元， 以及用于访问（115,130,135）存储器单元以读取/修改其状态的装置。 所述多个中的至少一个存储单元（FMC）用作检测器存储单元，并且提供与至少一个检测器存储单元可操作地相关联的控制装置（145），所述控制装置用于建立数据的潜在损失 基于所检测到的至少一个检测器存储单元的第一状态存储在所述多个存储单元中。

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